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Copper-based metal polishing solution and method for manufacturing semiconductor device

a technology of metal polishing solution and semiconductor device, which is applied in the direction of polishing compositions, semiconductor/solid-state device testing/measurement, instruments, etc., can solve the problem of low flatness

Inactive Publication Date: 2002-07-09
KK TOSHIBA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

It is another object of the present invention to provide a method for manufacturing a semiconductor device, in which a trench and / or an opening is formed in an insulating film on a semiconductor substrate, and an interconnection material film deposited on the insulating film and consisting of copper (Cu) or a copper alloy (Cu alloy) can be etched back within a short time period and at the same time a buried interconnecting layer whose surface is level with the surface of the insulating film can be formed.
It is still another object of the present invention to provide a method for manufacturing a semiconductor device, in which a trench and / or an opening is formed in an insulating film on a semiconductor substrate, an interconnection material film deposited on the insulating film and consisting of Cu or a Cu alloy can be etched back within a short time period to form a buried interconnecting layer whose surface is level with the surface of the insulating film, and the surface of the insulating film and the like after the etch back can be cleaned well.

Problems solved by technology

Unfortunately, the above polishing solution has the following problem since there is no difference between the Cu film dissolution velocity of the polishing solution during dipping and that during polishing.
This makes it difficult to form an interconnecting layer whose surface is level with the surface of the insulating film, resulting in a low flatness.

Method used

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  • Copper-based metal polishing solution and method for manufacturing semiconductor device
  • Copper-based metal polishing solution and method for manufacturing semiconductor device
  • Copper-based metal polishing solution and method for manufacturing semiconductor device

Examples

Experimental program
Comparison scheme
Effect test

example 1

First, as in FIG. 8A, a 1000 nm thick SiO.sub.2 film 22 as an insulating interlayer was deposited by a CVD process on a silicon substrate 21 on the surface of which diffusion layers such as a source and a drain (not shown) were formed. Thereafter, a plurality of trenches 23, 500 nm in depth, having a shape corresponding to an interconnecting layer were formed in the SiO.sub.2 film 22 by photoetching. As shown in FIG. 8B, a 15 nm thick TiN barrier layer 24 and a 600 nm thick Cu film 25 were deposited in this order by sputter vapor deposition on the SiO.sub.2 film 22 including the trenches 23.

Subsequently, the substrate 21, FIG. 8B, was held upside down by the substrate holder 5 of the polishing apparatus discussed earlier with reference to FIG. 1. A load of 300 g / cm.sup.2 was applied from the support shaft 4 of the holder 5 to the substrate toward the polishing pad 2 which was covered on the turntable 1 and consisted of SUBA800 (tradename) manufactured by Rodel Nitta Corp. While the ...

example 2

First, as in FIG. 13A, an 800 nm thick SiO.sub.2 film 22 and a 200 nm thick Si.sub.3 N.sub.4 film 27 were deposited in this order to form an insulating interlayer by a CVD process on a silicon substrate 21 on the surface of which diffusion layers such as a source and a drain (not shown) were formed. Thereafter, a plurality of trenches 23, 500 nm in depth, having a shape corresponding to an interconnecting layer were formed in the Si.sub.3 N.sub.4 film 27 and the SiO.sub.2 film 22 by photoetching. As shown in FIG. 13B, a 15 nm thick TiN barrier layer 24 and a 600-nm thick Cu film 25 were deposited in this order by sputter vapor deposition on the Si.sub.3 N.sub.4 film 27 including the trenches 23.

Subsequently, the substrate 21, FIG. 13B, was held upside down by the substrate holder 5 of the polishing apparatus discussed earlier with reference to FIG. 1. A load of 300 g / cm.sup.2 was applied from the support shaft 4 of the holder 5 to the substrate toward the polishing pad 2 which was c...

example 3

First, as in FIG. 14A, a 1000 nm thick Si.sub.3 N.sub.4 film 27 as an insulating interlayer was deposited by a CVD process on a silicon substrate 21 on the surface of which diffusion layers such as a source and a drain (not shown) were formed. Thereafter, a plurality of trenches 23, 500 nm in depth, having a shape corresponding to an interconnecting layer were formed in the Si.sub.3 N.sub.4 film 27 by photoetching. As shown in FIG. 14B, a 600 nm thick Cu film 25 was deposited on the Si.sub.3 N.sub.4 film 27 including the trenches 23 by sputter vapor deposition.

Subsequently, the substrate 21, FIG. 14B, was held upside down by the substrate holder 5 of the polishing apparatus discussed earlier with reference to FIG. 1. A load of 400 g / cm.sup.2 was applied from the support shaft 4 of the holder 5 to the substrate toward the polishing pad 2 which was covered on the turntable 1 and consisted of SUBA800 (tradename) manufactured by Rodel Nitta Corp. While the turntable 1 and the holder 5 w...

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Abstract

Disclosed is a copper-based metal polishing solution which hardly dissolves a Cu film or a Cu alloy film when the film is dipped into the solution, and has a dissolution velocity during polishing several times higher than that during dipping. This copper-based metal polishing solution contains at least one <DEL-S DATE="20020709" ID="DEL-S-00001" / >organic<DEL-E ID="DEL-S-00001" / > acid selected from aminoacetic acid and <DEL-S DATE="20020709" ID="DEL-S-00002" / >amidosulfuric<DEL-E ID="DEL-S-00002" / > <INS-S DATE="20020709" ID="INS-S-00001" / >aminosulfuric <INS-E ID="INS-S-00001" / >acid, an oxidizer, and water.

Description

BACKGROUND OF THE INVENTION1. Field of the InventionThe present invention relates to a copper-based metal polishing solution and a method for manufacturing a semiconductor device.2. Description of the Related ArtA polishing solution for a Cu film or a Cu-alloy film, which consists of a slurry of amine-based colloidal silica or a slurry added with K.sub.3 Fe(CN).sub.6, K.sub.4 (CN).sub.6, or Co(NO.sub.3).sub.2, is disclosed in J. Electrochem. Soc., Vol. 138, No. 11, 3460 (1991), VMIC Conference, ISMIC-101 / 92 / 0156 (1992) or VMIC Conference, ISMIC-102 / 93 / 0205 (1993).Unfortunately, the above polishing solution has the following problem since there is no difference between the Cu film dissolution velocity of the polishing solution during dipping and that during polishing.In the formation of an interconnecting layer as one manufacturing step of semiconductor devices, an etch-back technique is employed in order to remove steps from the device surface. This etch-back technique is a method i...

Claims

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Application Information

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Patent Type & Authority Patents(United States)
IPC IPC(8): C09G1/02C09G1/00H01L21/02H01L21/321C23F3/06
CPCC09G1/02C23F3/06H01L21/3212H01L21/7684H01L22/26C23F1/18
Inventor HIRABAYASHI, HIDEAKIHIGUCHI, MASATOSHI
Owner KK TOSHIBA