Interoperability with multiple instruction sets

Inactive Publication Date: 2012-03-13
ARM LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0020]It is an object of the invention to improve the capabilities of

Problems solved by technology

However, as described below, this technique requires additional program instruction words, which in turn require extra time during preparation of the software and extra memory space to store the p

Method used

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  • Interoperability with multiple instruction sets
  • Interoperability with multiple instruction sets
  • Interoperability with multiple instruction sets

Examples

Experimental program
Comparison scheme
Effect test

Example

[0042]FIG. 1 is a schematic diagram of a data processing apparatus having a processor core 10 coupled to a memory system 20.

[0043]The processor core 10 includes a register bank 30, a Booths multiplier 40, a barrel shifter 50, a 32-bit arithmetic logic unit (ALU) 60 and a write data register 70. Between the processor core 10 and the memory system 20 are: an instruction pipeline 80, a multiplexer 90, a first instruction decoder 100, a second instruction decoder 110, and a read data register 120.

[0044]A program counter (PC) register 130, which is part of the processor core 10, is shown addressing the memory system 20. A program counter controller 140 serves to increment the program counter value within the program counter register 130 as each instruction is executed and a new instruction must be fetched for the instruction pipeline 80. Also, when a branch instruction is executed, the target address of the branch instruction is loaded into the program counter 130 by the program counter ...

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PUM

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Abstract

Data processing apparatus comprising: a processor core having means for executing successive program instruction words of a predetermined plurality of instruction sets; a data memory for storing program instruction words to be executed; a program counter register for indicating the address of a next program instruction word in the data memory; means for modifying the contents of the program counter register in response to a current program instruction word; and control means, responsive to one or more predetermined indicator bits of the program counter register, for controlling the processor core to execute program instruction words of a current instruction set selected from the predetermined plurality of instruction sets and specified by the state of the one or more indicator bits of the program counter register.

Description

RELATED APPLICATIONS[0001]This is a divisional of application Ser. No. 08 / 477,781 filed on Jun. 7, 1995 now U.S. Pat. No. 5,758,115.BACKGROUND OF THE INVENTION[0002]1. Field of the Invention[0003]This invention relates to the field of data processing, and in particular to data processing using multiple sets of program instruction words.[0004]2. Description of the Prior Art[0005]Data processing systems operate with a processor core acting under control of program instruction words which when decoded serve to generate core control signals to control the different elements in the processor to perform the necessary operations to achieve the processing specified in the program instruction word.[0006]It is known to provide systems that execute program instruction words from two or more instruction sets, with means being provided to switch between use of the different instruction sets. The VAX11 computers of Digital Equipment Corporation have a VAX instruction mode and a compatibility mode...

Claims

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Application Information

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IPC IPC(8): G06F9/30G06F9/318G06F9/32G06F9/38G06F9/42
CPCG06F9/30196G06F9/321G06F9/3822G06F9/30181
Inventor NEVILL, EDWARD COLLES
Owner ARM LTD
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