Interoperability with multiple instruction sets

Abstract

Data processing apparatus comprising: a processor core having means for executing successive program instruction words of a predetermined plurality of instruction sets; a data memory for storing program instruction words to be executed; a program counter register for indicating the address of a next program instruction word in the data memory; means for modifying the contents of the program counter register in response to a current program instruction word; and control means, responsive to one or more predetermined indicator bits of the program counter register, for controlling the processor core to execute program instruction words of a current instruction set selected from the predetermined plurality of instruction sets and specified by the state of the one or more indicator bits of the program counter register.

Description

RELATED APPLICATIONS[0001]This is a divisional of application Ser. No. 08 / 477,781 filed on Jun. 7, 1995 now U.S. Pat. No. 5,758,115.BACKGROUND OF THE INVENTION[0002]1. Field of the Invention[0003]This invention relates to the field of data processing, and in particular to data processing using multiple sets of program instruction words.[0004]2. Description of the Prior Art[0005]Data processing systems operate with a processor core acting under control of program instruction words which when decoded serve to generate core control signals to control the different elements in the processor to perform the necessary operations to achieve the processing specified in the program instruction word.[0006]It is known to provide systems that execute program instruction words from two or more instruction sets, with means being provided to switch between use of the different instruction sets. The VAX11 computers of Digital Equipment Corporation have a VAX instruction mode and a compatibility mode...

AI Technical Summary

Benefits of technology

[0020]It is an object of the invention to improve the capabilities of data processing apparatus to switch between multiple instruction sets.

[0034]Preferably, program instruction words of the first instruction set are X-bit program instruction words; and program instruction words of the second instruction set are Y-bit program instruction words; where Y is different to X. In this way, a common processor core can be programmed with either an instruction set having longer program instruction words and allowing potentially more powerful and involved instructions, or an instruction set having shorter program instruction words, thus saving memory space where a potentially more limited instruction set can be tolerated.

Problems solved by technology

However, as described below, this technique requires additional program instruction words, which in turn require extra time during preparation of the software and extra memory space to store the program instruction words.

However, the process has a five instruction overhead per routine which is called from a different instruction set, and it also introduces a significant processing overhead.

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