Process for manufacturing 0.8 micron silicon bipolar CMOS integrated circuit
A manufacturing process and process technology, which is applied in the field of 0.8 micron silicon bipolar complementary metal oxide semiconductor integrated circuit manufacturing process, can solve problems such as high cost and complicated process flow, and achieve high gain effect
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[0024] The technical solution of the present invention will be further described below in conjunction with the embodiments.
[0025] The process flow of manufacturing process of the present invention is as follows, with reference to Fig. 1, wherein main feature is also to form deep P-type well in N well; The gate oxide layer of high-voltage device and low-voltage device is finished in the same oxidation step; An isolated NMOS device and a bipolar NPN device are formed on the N well of the P well.
[0026] As shown in Figure 1, the process includes the following steps:
[0027] S11. Forming an N well and a P well on a P-type substrate by using ion implantation and a thermal push process. In this embodiment, the step of making the double wells specifically includes: initial oxygen; using photoresist to locate the N well region and the P well; N well ion implantation; P well ion implantation; double well advance. Referring to FIG. 2 for the above steps, these steps are the same...
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