Input buffer circuit for stabilizing logic converting point

Abstract

When voltage of power supply, procedure for manufacturing semiconductor and temperature occur change, the buffer circuit for converting TTL to CMOS accomplishes function and reaches purpose for stabilizing logic transition point of I / O voltage. Adding a bias unit to the circuit, the invention generates a control signal in negative feedback for the input buffer in order to implement control and modulation. The invention stabilizes logic transition point of I / O voltage in order to avoid following situations happening: too large difference between transmission time from low to high level (tLH) and transmission time from high to low level (tHL); becoming worse to allowance of noise at high and low levels; even causing error transition of signal. The invention guarantees normal operation of CMOS circuit.

Description

technical field [0001] The present invention relates to a circuit for a TTL to CMOS input buffer. The circuit of this buffer can keep the logic transition point of the input / output voltage of this buffer stable under the variation of power supply voltage, semiconductor process, and temperature. Background technique [0002] As we all know, TTL is a widely used transistor-transistor-logic circuit, which is composed of multiple bipolar junction transistors (BJT: Bipolar Junction Transistor). Hole" (hole) these two kinds of carriers (carrier) to conduct current electronic components. Its advantage is high speed, but consumes a lot of power, so when the component density increases, the heat dissipation problem becomes a major obstacle for BJT application. Therefore, it is mainly used in high power devices and logic circuits requiring high speed. [0003] CMOS is the most popular transistor in the current large-scale integrated circuit (VLSI) system. It not only has high circu...

AI Technical Summary

Problems solved by technology

[0018] The large variation in the input / output voltage logic transition point of the TTL-to-CMOS buffer described above will cause the buffer's low-to-high transition time (tLH) and high-to-low transition time The time (tHL) difference is too large, and the noise margin of high and low levels becomes worse, and in severe cases, it may even lead to signal conversion errors, resulting in the failure of the entire CMOS circuit and other shortcomings and limitations

This is the significant shortcoming and limitation of this kind of buffer circuit design of the prior art

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