Nitride offset spacer to minimize silicon recess by using poly reoxidation layer as etch stop layer

Abstract

A method of forming a semiconductor device provides a gate electrode (22) on a substrate (20) and forms a polysilicon reoxidation layer (26) over the substrate (20) and the gate electrode (22). A nitride layer (28) is deposited over the polysilicon reoxydation layer (26) and anisotropically etched. The etching stops on the polysilicon reoxidation layer (26), with nitride offset spacers (30) being formed on the gate electrode (22). The use of the polysilicon reoxidation layer (26) as an etch stop layer prevents the gouging of the silicon substrate (20) underneath the nitride layer (28), while allowing the offset spacers (30) to be formed.

Description

technical field [0001] The present invention relates to the field of semiconductor device fabrication, and more particularly, to the use of offset spacing during the formation of semiconductor devices. Background technique [0002] U.S. Patent No. US-A-5 912 188 and No. US-A-6 165 831 disclose a semiconductor device manufacturing method using an etch stop layer on a substrate to prevent damage to the substrate during the etching process of the cover layer . [0003] As the minimum feature size of semiconductor integrated circuits shrinks, the distance between the source and drain regions becomes smaller. The reduced spacing between the source and drain regions for the field effect transistor results in short channel effects such as punch-through effects, reduction in source-to-drain breakdown voltage, reduction in threshold voltage, and subthreshold Swing (sub-thresholdswing) increase. To mitigate this short channel effect, the semiconductor industry continues to idealize...

AI Technical Summary

Problems solved by technology

This is because silicon damage will also increase the joint depth, which is not ideal in today's technology trend of seeking shallow depth joints.

In addition, due to the occurrence of damage during the formation of the offset space, there will be an adverse effect on the overlap capacitance

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