Mould set structure with multiple package and fins

Abstract

The invention includes a baseboard, a chip, complex number chip scale package structures and a heat sink. The chip scale package structure is fixed on circumference of the base board. The chip is located between chip scale package structures. The backside of chip scale package is higher than non-active side of chip to support heat sink. The heat sink has a cooling surface and a binding face. The binding face includes a central convex area and a peripheral flat area. The peripheral flat area is bound with the backside of chip scale package structure, and the central convex area is thermally coupled with non active side of chip.

Description

technical field [0001] The present invention relates to a multi-package module structure (Multi Package Module, MPM), in particular to a multi-package module structure with heat sinks. Background technique [0002] With the development trend of light, thin, short, and small semiconductor packages, integrating multiple package units in a single module (ie, multi-package module structure, MPM) is one of the development trends, because these packages are It is very close to a substrate, so the problem of heat dissipation must be solved. A known multi-chip packaging structure with heat dissipation components, as disclosed in Taiwan Patent Publication No. 558814, at least includes a substrate, a plurality of packages and a plurality of solder balls, the substrate has a substrate surface and corresponding A back surface of a substrate, the packages are disposed on the surface of the substrate, each of the packages includes at least one chip and a packaging material, wherein the p...

AI Technical Summary

Problems solved by technology

A known multi-chip packaging structure with heat dissipation components, as disclosed in Taiwan Patent Publication No. 558814, at least includes a substrate, a plurality of packages and a plurality of solder balls, the substrate has a substrate surface and corresponding A back surface of a substrate, the packages are disposed on the surface of the substrate, each of the packages includes at least one chip and a packaging material, wherein the packaging material covers the chip, and at least one of the packages includes at least one heat dissipation member , wherein the heat dissipation member is arranged on at least one chip, and the solder balls are arranged on the back surface of the substrate. Since the heat dissipation member is individually arranged on the chip, not only the manufacturing process is relatively complicated, but also the area of ​​the heat sink cannot be effectively enlarged.

[0003] Please refer to FIG. 1 , another known multi-package module structure 100 with heat sink includes a substrate 110, a semiconductor chip 120, a plurality of chip scale package structures 130 (Chip Scale Package, CSP), a dummy Chip 140 and a flat heat sink 150, wherein the substrate 110 has an upper surface 111 and a lower surface 112, the lower surface 112 of the substrate 110 is combined with a plurality of solder balls 160, the semiconductor chip 120 has an active surface 121 And a non-active surface 122, the active surface 121 is formed with a plurality of bumps 123, combined with flip-chip on the upper surface 111 of the substrate 110, each chip size package structure 130 has a bonding surface 131 and a back surface 132 , the bonding surface 131 is formed with a plurality of external terminals 133 to be combined with the upper surface 111 of the substrate 110. Since the backsides 132 of the chip-scale packaging structures 130 are higher than the non-active surface 122 of the semiconductor chip 120, it is necessary to The dummy chip 140 is bonded to the non-active surface 122 of the semiconductor chip 120, so that the dummy chip 140 is at the same height as the chip size packaging structures 130, and the flat heat sink 150 can be bonded to the dummy chip 140. and these chip-scale package structures 130, so the manufacturing process of the multi-package module structure 100 needs to include the grinding, cutting and pasting of the virtual chip 140, which is relatively complicated and costly

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