Method for the manufacture of a non-volatile memory device and memory device thus obtained

Abstract

The invention relates to a method of processing a non-volatile memory cell (50) comprising a double gate stack and a single access gate. This approach combines treating the access gate with a drain implant separate from the source implant in a self-aligned manner. The method of the present invention does not require mask alignment sensitivity and enables self-aligned implantation of extended drains for erasing memory devices. Furthermore, the method provides a way to perform separate drain and source implants with different dopings without using additional masks.

Description

technical field [0001] The present invention relates to the field of non-volatile semiconductor memory. Background technique [0002] Non-volatile memory (NVM) is widely used in a variety of commercial and military electronics and equipment, such as cellular phones, radios, and digital cameras. The market for these electronic devices continues to demand devices with lower voltage, lower power consumption, and reduced chip size. [0003] The flash memory or flash memory cell includes a MOSFET with a floating gate between the control gate and the channel region. With the improvement of manufacturing technology, the size of the floating gate has been reduced to the order of nanometers. These devices are essentially miniature EEPROM cells in which electrons (or holes) are injected into nanofloating gates by tunneling through an oxide barrier layer. The charge stored in the floating gate changes the device threshold voltage. Stacked gate technology is employed in the fabricat...

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Problems solved by technology

[0009] Another disadvantage of the method described above is that an additional masking step must be performed when different doping is required in the source and drain regions

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