Method for instruction buffering based on SPM in embedded system
A technology of embedded system and implementation method, applied in the direction of concurrent instruction execution, sustainable building, energy-saving computing, etc., can solve the problem of inability to enter the sleep state, and achieve the effects of high speed, reduced energy consumption, and low energy consumption
Inactive Publication Date: 2009-10-14
ZHEJIANG UNIV
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Problems solved by technology
[0018] The power management of ScratchPad Memory can be simply completed by setting the bits of the corresponding registers, so as to save the energy consumption of the running embedded system as much as possible. This design is also beyond the reach of DRAM, because DRAM needs to ensure Only by refreshing can the content stored in it be guaranteed, and it cannot enter the dormant state
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[0045] The present invention is an implementation method of SPM-based instruction buffering in an embedded system, and its specific implementation process will be described below in conjunction with the accompanying drawings.
[0046] 1) SPM space division:
[0047] According to the characteristics of ScratchPad Memory, the SRAM space is divided into blocks with a size of 4k as the smallest unit. There are visible differences in the physical characteristics of each bank of ScratchPad SRAM. Different banks have different access speeds. These banks can be divided into fast banks with fast access speeds and slow banks with slow access speeds. In order to reduce internal fragmentation, the division of space in each bank is not completely consistent.
[0048] For an SPM with m fast banks and n slow banks, the bank numbers of the fast banks are QB0 to QBm-1, and the space is divided into logical blocks each with a size of 4k, which is the minimum physical size of ScratchPadSRAM Us...
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The invention discloses a realization method for instruction buffering based on SPM in a built-in system. The method of the invention combines the characteristic that the SPM is arranged on a built-in processor chip, carries out the division of the space of the SPM and leads the instructions of the program to stay on the SPM. The method of the invention realizes the effective use of the SPM, sufficiently uses the characteristic of fast speed of the SPM and improves the efficiency of program execution. The method of the invention realizes effective use of the SPM, sufficiently uses the characteristic of fast speed of the SPM and improves the efficiency of program execution. The use of the SPM by the invention is beneficial to reducing the energy consumption which is caused by the memory access during the running process of the program.
Description
technical field [0001] The invention relates to the technical field of embedded systems, in particular to an implementation method of an SPM-based instruction buffer in an embedded system. Background technique [0002] As embedded systems are more and more known and understood by people, the requirements for the performance, operating speed, energy consumption and other aspects of embedded systems are also getting higher and higher. In order to improve the running speed of the program running on the embedded system, people have higher and higher requirements on the embedded operating system while continuously developing and improving the hardware. [0003] Because of the complexity of the embedded environment, people require the operating system on it to have special planning and customization, and do not want to have only commonality and no individuality. For example, some embedded devices only need to complete relatively certain tasks, so the operating system on it may on...
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IPC IPC(8): G06F9/38G06F12/02
CPCY02B60/1225Y02D10/00
Inventor 陈天洲胡威施青松严力科谢斌黄江伟章铁飞冯德贵项凌祥陈剑
Owner ZHEJIANG UNIV