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Lateral semiconductor device using trench structure and method of manufacturing the same

A semiconductor and trench technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve the problems of difficult practical operation, length limitation, concentration reduction, etc., to increase the contact area and reduce the on-resistance. Effect

Inactive Publication Date: 2009-12-16
SII SEMICONDUCTOR CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, this method also has a limitation on the length, and in addition, there is a risk that the concentration of the source region 001 or the drain region 002 is reduced due to excessive impurity diffusion.
Therefore, this method is difficult to practice
That is, it is difficult to increase the contact area in the prior art without changing the element area to reduce the on-resistance of the MOS transistor
[0007] (2) The second problem is that there is a limit to the groove depth
Therefore, the trench cannot be deeper than well region 005

Method used

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  • Lateral semiconductor device using trench structure and method of manufacturing the same
  • Lateral semiconductor device using trench structure and method of manufacturing the same
  • Lateral semiconductor device using trench structure and method of manufacturing the same

Examples

Experimental program
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Effect test

Embodiment 1

[0024] figure 1 A to 1C show typical embodiments of the present invention. here, figure 1 A is the floor plan, figure 1 B is along figure 1 A cross-sectional view taken along line 1A-1A'; and figure 1 C is along figure 1 Perspective view obtained by line 1A-1A' and line 1B-1B' of A. here, in figure 1 In A, the gate electrode 003 and the gate insulating film 004 on the trench are transparent for easy observation. Thick lines indicate the edges of the gate electrode 003 . and, figure 1 C is a view seen from source region 001. In this figure, metal interconnections are not omitted in order to three-dimensionally show the source and drain structures. The figure shows a symmetrical structure with the line 1A-1A' as its center. Therefore, the figure seen from the drain region 002 is the same as figure 1 C is the same. Note that the selection of symmetrical structures in the description of the embodiments of the present invention is easy to understand; however, ...

Embodiment 2

[0037] Figure 5 An embodiment of the invention is shown, which has a DDD structure. Embodiment 2 differs from Embodiment 1 only in that: before forming the source region 001 and the drain region 002, the third trench region 015 is opened, and a low-level diffusion region 011 is formed, which includes the drain region formed in a subsequent step. District 002. Therefore, a high drive performance MOS transistor with high withstand voltage and low on-resistance is completed.

Embodiment 3

[0039] Image 6 An embodiment of the invention is shown, which has an LDMOS structure. Embodiment 3 differs from Embodiment 1 only in that: before forming the source region 001 and the drain region 002, the second trench region 014 is opened, and the body region 012 is formed, which does not include the drain region formed in a subsequent step 002, but added source area 001. Therefore, a high drive performance MOS transistor with high withstand voltage and low on-resistance is completed.

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PUM

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Abstract

Provided is a lateral trench MOS transistor, wherein a trench extending to a source region and a drain region is provided parallel to a gate length direction, a gate oxide is provided on the trench, and a well region is provided in the trench by using inclined ion implantation. Underneath the sink region and the source and drain regions, the gate electrode is disposed on the gate oxide, and by using inclined ion implantation, the source and drain regions are disposed at the bottom of the concave portion of the trench self-aligned with the gate electrode on the same plane as the surface.

Description

technical field [0001] The present invention relates to a semiconductor device including a lateral MOS transistor requiring high driving performance and a method of manufacturing the semiconductor device. Background technique [0002] Small geometries of MOS transistors can be fabricated without degrading capacity by utilizing progressively finer processing techniques. This tendency also applies to semiconductor elements requiring high driving performance without exception. In order to achieve high driving performance, attempts have been made to reduce the on-resistance of an element per unit planar area using fine processing techniques. However, the fact that the reduction in withstand voltage caused by the miniaturization of semiconductor elements hinders further improvement in driving performance. In order to eliminate the trade-off between miniaturization and withstand voltage, semiconductor devices having various structures have been proposed. A trench gate MOS trans...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/78H01L21/336
Inventor 理崎智光
Owner SII SEMICONDUCTOR CORP