Chip package structure

A chip packaging and chip technology, applied in the direction of electrical components, electrical solid devices, circuits, etc., can solve the problems of contamination of the electrical connection area of ​​the bonding wire, transportation or storage, and the way that circuit substrates cannot be stacked.
CN101000899AInactive Publication Date: 2007-07-18CHIPMOS TECH INC
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
CHIPMOS TECH INC
Publication Date
2007-07-18
Estimated Expiration
Not applicable · inactive patent

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Abstract

The invention relates to one kind of chip encapsulation structure, which includes a first chip, a circuit substrate and a two-stage thermosetting adhesive layer. The first chip has a first super-surface, a first side and a first undersurface; the circuit substrate has a super-surface and an undersurface, and it links with the first chip by the electric properties. In addition, the two-stage thermosetting adhesive layer lies on the substrate, and the layer has the first and the second adhesive surface, the partial first adhesive surface bonds with the first undersurface, and the second adhesive surface links with the super-surface of the substrate, making the first chip adhesion to the super-surface of the substrate. The first adhesive surface roughly parallels with second adhesive surface, and the two-stage thermosetting adhesive layer has the edge which diminishes its thickness gradually.
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Description

technical field

[0001] The present invention relates to a semiconductor device, and in particular to a chip packaging structure. Background technique

[0002] In the semiconductor industry, the production of integrated circuits (IC) is mainly divided into three stages: wafer manufacturing, IC process, and IC package. Among them, the chip (chip) is completed through the steps of wafer fabrication, circuit design, mask (mask) fabrication, and wafer dicing, and each chip formed by wafer dicing is passed through the bonding pad on the chip. After the bonding pad is electrically connected to the external signal, the chip can be encapsulated with an encapsulant material. The purpose of packaging is to prevent the chip from being affected by moisture, heat, and noise, and to provide a medium for the electrical connection between the chip and the external circuit, thus completing the packaging step of the integrated circuit.

[0003] Please refer to FIG. 1 , which is a schematic c...

Claims

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