Chip package structure

A chip packaging and chip technology, applied in the direction of electrical components, electrical solid devices, circuits, etc., can solve the problems of contamination of the electrical connection area of ​​the bonding wire, transportation or storage, and the way that circuit substrates cannot be stacked.

Inactive Publication Date: 2007-07-18
CHIPMOS TECH INC
View PDF0 Cites 17 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] The purpose of the present invention is to provide a chip packaging structure to solve the problem of the overflow of the adhesive layer and the pollution of the electrical connection area of ​​the welding wire
[0009] Another object of the present invention is to provide a chip packaging structure to solve the problem that the circuit substrates with adhesive layers cannot be transported or stored in a stacked manner

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Chip package structure
  • Chip package structure
  • Chip package structure

Examples

Experimental program
Comparison scheme
Effect test

no. 1 example

[0081] Please refer to FIG. 3 , which is a schematic cross-sectional view of a chip package structure according to a first embodiment of the present invention. The chip packaging structure 300 of the first embodiment includes a first chip 310 , a circuit substrate 320 and a two-stage thermosetting adhesive layer 330 . The first chip 310 has a first upper surface 312, a first side 314 and a first lower surface 316, the circuit substrate 320 has a substrate upper surface 322 and a substrate lower surface 324, and the first chip 310 and the circuit substrate 320 Phase electrical connection. In addition, a two-stage thermosetting adhesive layer 330 is located on the upper surface 322 of the substrate. The two-stage thermosetting adhesive layer 330 has a first adhesive surface 332 and a second adhesive surface 334, and part of the first adhesive surface 332 is bonded to the first lower surface 316. , the second adhesive surface 334 is bonded to the upper surface 322 of the substra...

no. 2 example

[0087] Please refer to FIG. 4 , which is a schematic cross-sectional view of a chip package structure according to a second embodiment of the present invention. The main difference between the second embodiment and the first embodiment lies in that the shape of the two-stage thermosetting adhesive layer 430 of the chip packaging structure 400 is different. The two-stage thermosetting adhesive layer 430 further includes an annular protrusion 436 surrounding the periphery of the first side 414, and the first side 414 is joined to the annular protrusion 436, and the annular protrusion 436 adjacent to the first side 414 A top surface 436a is substantially perpendicular to the first side 414 .

[0088] The reason for the formation of the ring-shaped protrusion 436 is the progress time of the two-stage thermosetting adhesive layer 430 from the state of the A-stage thermosetting adhesive layer to the state of the B-stage thermosetting adhesive layer. If the time at a certain designe...

no. 3 example

[0090] Please refer to FIG. 5 , which is a schematic cross-sectional view of a chip package structure according to a third embodiment of the present invention. The main difference between the third embodiment and the above-mentioned embodiments is that the chip package structure 500 is a multi-chip package structure, which further includes a second chip 560 and an adhesive layer 570 . The second chip 560 has a second upper surface 562 , a second lower surface 564 and a plurality of bonding pads 566 on the second upper surface 562 . The material of the adhesive layer 570 can be the same as that of the two-stage thermosetting adhesive layer 530. The adhesive layer 570 is disposed between the first wafer 510 and the second wafer 560, wherein the second lower surface 564 of the second wafer 560 is connected to the second wafer 560 by the adhesive layer 570. The first upper surface 512 of the first wafer 510 is bonded. In addition, the chip package structure 500 further includes a...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

No PUM Login to view more

Abstract

The invention relates to one kind of chip encapsulation structure, which includes a first chip, a circuit substrate and a two-stage thermosetting adhesive layer. The first chip has a first super-surface, a first side and a first undersurface; the circuit substrate has a super-surface and an undersurface, and it links with the first chip by the electric properties. In addition, the two-stage thermosetting adhesive layer lies on the substrate, and the layer has the first and the second adhesive surface, the partial first adhesive surface bonds with the first undersurface, and the second adhesive surface links with the super-surface of the substrate, making the first chip adhesion to the super-surface of the substrate. The first adhesive surface roughly parallels with second adhesive surface, and the two-stage thermosetting adhesive layer has the edge which diminishes its thickness gradually.

Description

technical field [0001] The present invention relates to a semiconductor device, and in particular to a chip packaging structure. Background technique [0002] In the semiconductor industry, the production of integrated circuits (IC) is mainly divided into three stages: wafer manufacturing, IC process, and IC package. Among them, the chip (chip) is completed through the steps of wafer fabrication, circuit design, mask (mask) fabrication, and wafer dicing, and each chip formed by wafer dicing is passed through the bonding pad on the chip. After the bonding pad is electrically connected to the external signal, the chip can be encapsulated with an encapsulant material. The purpose of packaging is to prevent the chip from being affected by moisture, heat, and noise, and to provide a medium for the electrical connection between the chip and the external circuit, thus completing the packaging step of the integrated circuit. [0003] Please refer to FIG. 1 , which is a schematic c...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/31
CPCH01L2924/15311H01L2224/06135H01L2224/16H01L2224/48091H01L2224/73215H01L2224/0401H01L2224/73265H01L24/29H01L2224/32145H01L24/32H01L2224/32225H01L2224/4824H01L2924/14
Inventor 林俊宏
Owner CHIPMOS TECH INC
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap