Signal-to-interference ratio target value regulating method and device in outerloop power control
A technology of outer loop power control and adjustment method, which is applied in the direction of transmission control/equalization, advanced technology, climate sustainability, etc., and can solve the problems of increasing power consumption, slow reduction of SIRtar value, and slow decline of mobile station transmission power, etc. problem, to achieve the effect of accelerating the decline and reducing power loss
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Embodiment 1
[0065] Embodiment one (k=1, a=0.5, n=2)
[0066] Then the down-regulation steps of SIRtar in the two outer loop power control cycles of the first stage are: 0.5UpStep and 0.25UpStep respectively, and the number of outer loop power control cycles included in the second stage is:
[0067]
[0068] Assuming that an erroneous block is received in the Mth outer loop power control cycle, and the outer loop power control cycle after the Mth outer loop power control cycle continuously receives correct blocks, then the outer loop power control method of this embodiment adjusts the The adjustment curve is shown in Figure 2, including the following process:
[0069] In the Mth outer loop power control cycle, adjust the SIRtar to rise according to the rising step size UpStep;
[0070] Adjust the SIRtar drop by 0.5UpStep in the M+1th outer loop power control cycle, and adjust the SIRtar drop by 0.25UpStep in the M+2th outer loop power control cycle. This process is the first stage;
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Embodiment 2
[0076] Embodiment two (k=1 / 9, a=0.9, n=10)
[0077] Referring to the curve shown in Figure 3, the outer loop power control in this embodiment specifically includes the following processes:
[0078] In the Rth outer loop power control cycle, adjust the SIRtar up according to the up step UpStep;
[0079] In the R+1th to R+10th outer loop power control cycle, adjust the SIRtar down according to the corresponding step size, wherein, the downward adjustment step size in the R+ith outer loop power control cycle is 1 / 9*0.9 i *UpStep, the above i=1,...,10, this stage is the first stage;
[0080] In the R+11th to R+u2+10th outer loop power control cycle, the SIRtar is not adjusted, that is, the SIRtar is kept unchanged, and this stage is the second stage;
[0081] After the first R+u2+10, each outer loop power control cycle adjusts the SIRtar down according to the average down step DnStep;
[0082] In this adjustment process, no matter which outer loop power control cycle receives a...
Embodiment 3
[0086] After the SIRtar is adjusted according to the upward step UpStep, a downward adjustment process is started. In the first stage of the downward adjustment process, the adjustment value in the i (i=1,...,n3) outer loop power control cycle is Ci*UpStep, Ci >Cj>0(i
[0087] UpStep ≥ Σ i = 1 n 3 Ci * UpStep > n 3 * ( BLERtar - BLERmeas ) 1 - BLERtar * UpStep .
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