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A method for removing interweaving and speed match

A rate matching and deinterleaving technology, applied in digital transmission systems, electrical components, error prevention, etc., can solve the problems of increasing circuit area and power consumption, reducing the capacity of the first interleaving RAM, and achieving low power consumption and saving The effect of capacity, simple algorithm

Active Publication Date: 2007-12-12
ZTE CORP
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  • Abstract
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  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] The technical problem to be solved by the present invention is to provide a method for de-interleaving and de-rate matching, which solves the disadvantages of increasing the area and power consumption of the circuit caused by the current use of too large interleaving RAM for the first time. While reducing the capacity of the first interleaving RAM, the gate control clock is used for processing, which can save power consumption

Method used

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  • A method for removing interweaving and speed match
  • A method for removing interweaving and speed match
  • A method for removing interweaving and speed match

Examples

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no. 1 Embodiment approach

[0149] The first specific embodiment, as shown in Figure 2, comprises the following steps:

[0150] Step 210, judging the rate matching mode of the transmission channel, if it is the punching mode, then perform step 220; otherwise, perform step 230;

[0151] Step 220, perform the first deinterleaving process on the symbol sequence of the current frame of the transmission channel; execute step 260;

[0152] Step 230, calculate the parameter e value corresponding to the current symbol, and its write address symbol_addr in the first interleaving RAM;

[0153] Step 240, judging whether the e value corresponding to the current symbol is less than 0, if less than 0, then perform step 250, otherwise perform step 260;

[0154] Step 250, discard this symbol, and turn to the processing of the next symbol;

[0155] Step 260, write the above-mentioned processed symbols into the first interleaving RAM in sequence;

[0156] Step 270, if there are TTI symbol sequences subjected to punctur...

no. 2 Embodiment approach

[0158] As shown in Figure 3, it includes the following steps:

[0159] Step 310, judging the rate matching mode of the transmission channel, if it is the punching mode, then perform step 320; otherwise, perform step 330;

[0160] Step 320, perform the first deinterleaving process on the symbol sequence of the current frame of the transmission channel; execute step 390;

[0161] Step 330, judging whether the TTI of the current transmission channel is greater than 10ms, if not greater than 10ms, then execute step 340; otherwise execute step 360;

[0162] Step 340, calculating the parameter e value of the current symbol and its write address symbol_addr in the first interleaving RAM;

[0163] Step 350, if the e value corresponding to the current symbol is greater than 0, then directly register the current symbol, otherwise the current symbol and the last registered symbol are accumulated and registered; perform step 390;

[0164] Step 360, when the system is reset, clear the in...

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Abstract

A method for dispelling interlace and dispelling speed match, first according to the matching mode for speed of transmission channel, judges that whether or not actualize the stiletto transmission channel, if yes, the symbol serial of present frame of transmission channel is operated the first dispelling interlace; if no, the symbol serial of present frame of transmission channel is operated the first dispelling interlace, and at the same time the symbol serial of present frame of transmission channel is operated the repeating procession of dispelling byte; and then the processed symbol serial is written in the random memory of first interlace; at last if said first interlace random memory has the symbol serial of transmission channel and transmission time interval, and the dispelling stiletto process is done according to the interval symbol of transmission time. Using the invention, it can reduce the RAM capacity of first interlace, adopt the gate-control clock to process, and save the power consumption.

Description

technical field [0001] The invention relates to a method for deinterleaving and rate matching in a mobile communication system, in particular to a method for deinterleaving and rate matching in a downlink of a WCDMA (Wideband Code Division Multiple Access) communication system. Background technique [0002] In the downlink of the wireless communication system, the encoding and multiplexing processing of the transmission channel mainly includes CRC (Cyclic Redundancy Code, cyclic redundancy check code) addition, channel coding, rate matching, first interleaving, and transmission channel multiplexing Wait. The international standard 3GPP 25.212 of the third generation mobile communication system stipulates the transmission channel multiplexing processing structure of the downlink of the WCDMA communication system. [0003] For a detailed description of the multiplexing and coding of the downlink, please refer to the international standard 3GPP 25.212 of the third generation m...

Claims

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Application Information

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IPC IPC(8): H04L1/00
Inventor 袁学龙
Owner ZTE CORP
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