CPIC signal processing board

Abstract

The present invention provides a CPCI signal processing board, including at least two general processors, which mutually connect through a front-end bus, a north bridge chip, which connects with the processor through the front-end bus and with a shared memory and a CPCI bus, which connects the north bridge chip through a PCI bridge. The present invention is equipped with the following technology effects: the application of multi-slice general processors can compute parallel data in large scale and at the same time provide developers with a general software developing platform. The multi-slice general processor connects with the north bridge chip bu sharing the front-end bus and the north bridge chip connects with a shared memory, improving communication efficiency greatly and reducing communication delay.

Description

technical field [0001] The invention relates to the fields of computer architecture, parallel computing and industrial control computers, in particular, the invention relates to a signal processing board. Background technique [0002] The Compact PCI bus is a high-performance industrial bus developed based on the PCI electrical specification. [0003] The Compact PCI standard perfectly combines the standard features of peripheral component interconnection with a solid mechanical shape that supports embedded applications. It has the advantages of high speed, high reliability, durability, hot swappability, and strong versatility. It is specially designed for industrial environments And tailor-made, it has been widely promoted in many fields such as radar and sonar. [0004] Array signal processing is an important branch of modern signal processing. Its essence is to use spatially dispersed sensor arrays and multi-channel receivers to obtain multi-dimensional information such ...

AI Technical Summary

Problems solved by technology

However, this structure also has some disadvantages: firstly, since each processor is connected to a North Bridge chip, it not only increases the system cost, but also wastes the PCB space of the board; secondly, when multiple PowerPCs communicate, first The data to be processed by the local PowerPC processor will be taken out from the memory on the North Bridge chip, and then sent to the North Bridge chip directly connected to the processor, and then sent to the destination PowerPC through the PCI-X / PCIE bus interconnected between the North Bridge chips The connected north bridge chip is then sent to the destination PowerPC processor, and then sent to the memory of the north bridge chip connected to the destination PowerPC processor after the processor, which undoubtedly increases the delay of data transmission and has higher requirements for real-time performance Very disadvantageous in terms of array signal processing of the

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