Thickness reduced multi-chip stacking and packaging construction

Abstract

The present invention relates to thickness-reduced-multi-wafer-stacked package, and mainly includes an interval substrate and even numbers of pins of a line frame, a first wafer, a second wafer and a sealing colloid. Even numbers of first electrodes are formed on active surface of the first wafer, and are electric connected to parts of the pins. Even numbers of second electrodes are formed on active surface of the second wafer, and are electric connected to parts of the pins. The sealing colloid is used for combining the interval substrate, the pins, the first and the second wafers. In specific, the active surface of the first wafer clings down to the interval substrate, and the active surface of the second wafer clings up to the interval substrate. The first pins of the first wafer are not covered by the interval substrate, thus thickness of multi-wafer-forward stack can be reduced.

Description

technical field [0001] The present invention relates to a semiconductor chip stack package structure, in particular to a reduced thickness multi-chip stack package structure using a lead frame. Background technique [0002] In a multi-chip package structure (Multi-Chip Package, MCP), stacking a plurality of chips vertically to save package size is a fairly mature technology. However, spacers between the dies increase the overall package thickness. [0003] Please refer to FIG. 1 , which is a schematic cross-sectional view of a conventional multi-chip stack package structure. The existing conventional multi-chip package structure 100 utilizes a lead frame as a chip carrier, and includes a chip holder 111 and a plurality of pins 112, a first chip 120, a second chip 130 and a package with a lead frame. Colloid 140. The first wafer 120 and the second wafer 130 are stacked on the wafer holder 111 in a forward direction. The plurality of bonding wires 150 electrically connect ...

AI Technical Summary

Problems solved by technology

Therefore, the back side of the first chip 220 faces the back side of the second chip 230, and the lead frame needs to be turned over when electrically connecting to form the bonding wires 251 and 252, and the upper and lower surfaces of the pins 212 must form a double-sided plating layer 213, resulting in an increase in the cost of the lead frame and package

In addition, since the sealant 240 is not well bonded to the general electroplating layer, if the double-sided plating layer 213 covers an excessively large area, the interface between the sealant 240 and the pins 212 will be peeled off easily.

[0005] It can be seen that the above-mentioned existing multi-chip stacked package structure obviously still has inconvenience and defects in structure and use, and needs to be further improved urgently.

In order to solve the above-mentioned problems, the relevant manufacturers have tried their best to find a solution, but no suitable design has been developed for a long time, and the general products do not have a suitable structure to solve the above-mentioned problems. This is obviously related. The problem that the industry is eager to solve

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