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Method for removing clearance wall, metal semiconductor transistor parts and its making method

A spacer and semiconductor technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve problems affecting sheet resistance, nickel silicide damage, easily damaged metal silicide layers, etc.

Active Publication Date: 2008-03-26
UNITED MICROELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, the metal silicide layer is easily damaged, especially when the spacer is silicon nitride and the metal silicide layer is nickel silicide, the nickel silicide is easily damaged during etching, which affects the wafer acceptance test (wafer acceptance test) Sheet resistance in the project (sheet resistance)

Method used

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  • Method for removing clearance wall, metal semiconductor transistor parts and its making method
  • Method for removing clearance wall, metal semiconductor transistor parts and its making method
  • Method for removing clearance wall, metal semiconductor transistor parts and its making method

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Embodiment Construction

[0025] Please refer to FIG. 2 to FIG. 7 , which show cross-sectional schematic diagrams of a method for manufacturing semiconductor MOS transistor elements according to an embodiment of the present invention, wherein the same elements or parts are still represented by the same symbols. It should be noted that the drawings are for illustration purposes only and are not drawn to original scale.

[0026] The invention relates to a method of manufacturing NMOS, PMOS transistor elements or CMOS elements in integrated circuits. As shown in FIG. 2 , a semiconductor substrate is prepared, which generally includes a silicon layer 16 . The foregoing semiconductor substrate may be a silicon substrate or a silicon-on-insulator (SOI) substrate. An electrode such as a gate 12 is formed on the semiconductor substrate. A shallow junction source extension 17 and a shallow junction drain extension 19 are formed in the silicon layer 16 on both sides of the gate 12 . A channel 22 is separated ...

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Abstract

This invention discloses a method for removing gap walls, a method for manufacturing MOS transistor elements and MOS transistor elements, in which, a protection layer is deposited on a source / drain region, a substance layer on a grid and a gap wall before the gap wall is removed to make the thickness of the protection layer on the gap wall smaller than that on the substance layer, then part of the protection layer is removed to make its thickness on the gap wall almost zero and remains on the substance layer, therefore, the substance layer can be protected by the protection layer when removing the gap wall.

Description

technical field [0001] The invention relates to a semiconductor device process, in particular to the removal of spacers in the process of metal oxide semiconductor (MOS) transistor elements. Background technique [0002] As the semiconductor technology enters the deep submicron era, such as the technology below 65 nanometers (nm), it becomes increasingly important to increase the drive current of the MOS transistor element. In order to improve the performance of the device, the industry has developed the so-called "strained silicon (strained-silicon) technology". The movement force in the channel is increased, thereby achieving the purpose of making the MOS transistor operate faster. [0003] Basically, the strain of the silicon lattice can be achieved in the following two ways: The first way is to use the stress film formed around the transistor, such as the stress film (polystressor) deposited on the polysilicon gate or in the metal silicide layer. The contact etch stop ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/311H01L21/336H01L29/78
Inventor 周珮玉邹世芳廖俊雄
Owner UNITED MICROELECTRONICS CORP