Image display system and method for driving display component

Abstract

The invention provides an image display system which comprises a signal drive circuit, wherein, the signal drive circuit comprises a plurality of tandem shift registers which are controlled by a first clock signal and a second clock signal to generate corresponding drive signal in turn according to a start pulse signal; each shift register comprises a first clock input end, an input end, an output end and a drive end; the first clock input end is used to receive one of the first clock signal and the second clock signal; the input end receives a first pulse signal; the output end generates an output signal; the drive end generates a drive signal according to the received clock signal to drive a sublevel shift register; moreover, the output signal and the drive signal are generated at different time intervals.

Description

technical field [0001] The invention relates to a signal driving circuit and method, in particular to a signal driving circuit in an image display system and a method for driving a display component. Background technique [0002] A display panel in an image display system, such as a TFT-LCD panel, usually includes a display component, and the display component has a two-dimensional pixel array with a plurality of pixels. These pixels can be controlled by a plurality of data lines and a plurality of gate signal lines. A driving circuit composed of several shift registers (SR) connected in series is used to provide corresponding driving signals so that the gate signal lines can be activated sequentially. [0003] Generally speaking, each shift register (SR) includes an input terminal, an output terminal, a power supply terminal and several clock signal terminals. An output terminal of the shift register is connected to one gate signal line of the LCD array, and each gate sig...

AI Technical Summary

Problems solved by technology

Similarly, if the threshold voltage Vtn of the NMOS transistor 27 is also reduced, some leakage current will be caused to further reduce the gate voltage level of the NMOS transistor 28

When the gate voltage of the NMOS transistor 28 drops to a low voltage level, the gate of the NMOS transistor 22 may generate floating nodes (floating nodes) with unclear voltage levels, such as nodes F1-F3 in FIG. 1 , so that The gate of NMOS transistor 22 is easily coupled with XCK to cause coupling noise

These floating nodes with uncertain voltage levels may cause the gate voltage signal of the NMOS transistor 22 to be distorted, and cannot maintain a sufficient voltage level for a period of time, so that the output signal may not be provided to the next-stage shift register.

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