Dram

Abstract

The invention discloses a dynamic random access memory, in particular to a dynamic random access memory which can reduce writing operation power consumption. The dynamic random access memory of the invention provides a bit line isolating circuit of a control bit line isolating end and a complementary bit line isolating circuit of a control complementary bit line isolating end. The bit line or complementary bit line isolating circuit includes a bit line or complementary bit line node signal circuit and a bit line or complementary bit line isolating signal circuit. The bit line or complementary bit line isolating circuit generates the bit line or complementary bit line isolating signal. The bit line isolating end and the complementary bit line isolating end are respectively controlled by the bit line or complementary bit line isolating signal individually, so that only one of the bit lines or complementary bit lines on the same storage unit array is conducted at the same time, thereby reducing current power consumption on the bit line or complementary bit line, and further reducing the power consumption of entire dynamic random access memory.

Description

technical field [0001] The present invention relates to dynamic random access memory (DRAM), and more particularly to a dynamic random access memory that enables low power consumption of memory access operations. Background technique [0002] DRAM is a semiconductor memory widely used now. With the continuous development of high-density memory, the size of the storage unit is gradually reduced, and this trend makes the DRAM with a simple structure the first choice. The most widely used DRAM structure is the single-transistor DRAM. It consists of a storage capacitor and an access transistor. DRAM is widely used as main memory in home PCs, mainframe computers and workstations due to its low cost and high density. The existing DRAM design pays more attention to the dynamic power consumption of the circuit, which is used as an index to measure the superiority of the DRAM circuit. [0003] The CMOS Digital Integrated Circuit-Analysis and Design (Third Edition) published by El...

AI Technical Summary

Problems solved by technology

But the disadvantage of this design is that the bit line and complementary bit line of the same memory cell array are controlled by a unified isolation terminal. When only the bit line or complementary bit line in the memory cell array is required to be turned on, the same memory cell array The bit line or complementary bit line above will also be turned on due to the unified isolation terminal control, that is, the bit line or complementary bit line of the same memory cell array will always be turned on at the same time, such as figure 2 , Figure 4 shown, this increases unnecessary current dissipation on the bit line or complementary bit line

As the capacity of DRAM becomes larger and larger, and has reached a capacity of 1T today, the entire DRAM will increase considerable power consumption.

Images