Multiport and multi-channel embedded dynamic ram and operating method thereof

Abstract

The invention belongs to the integrated circuit technical field, in particular to an embedded dynamic random access memory with multiple ports and multiple channels and a memory operating method thereof. The memory comprises a plurality of memory cells; n transistors which are arranged in each memory cell (n is a natural number and larger than or equal to 2); a word line bit line pair arranged in each transistor, wherein, the bit line of each transistor can be connected with an input / output port; different transistors in the memory cell are positioned in the same floating body which is electrically isolated from surrounding; word line bit line pairs of different transistors are independent form each other, and can be selected synchronously or time-sharing, then, corresponding different transistors selected at the same time or time-sharing can read memory and refresh memory operation synchronously or time-sharing through corresponding ports. The refreshing operation and the reading operation are independent mutually, thereby improving the speed of reading operation of the embedded type dynamic random access memory, and meeting different power consumption requirements through regulating frequency of the refreshing operation.

Description

technical field [0001] The invention belongs to the technical field of microelectronics, and in particular relates to a multi-port, multi-channel embedded dynamic random access memory and a storage operation method thereof. Background technique [0002] Dynamic Random Access Memory (DRAM) is a memory device that can be used to store information. DRAMs are favored in some applications because they can be manufactured at very high densities fairly cheaply. Embedded dynamic random access memory (e DRAM) and other logic circuits are integrated in one chip, which can save a lot of buffers and I / O pressure points, so that it can have higher speed, smaller area and lower cost. power consumption. Since there is a built-in wide-bit data bus between the DRAM core and the logic circuit, this massive parallel processing capability enables embedded DRAM to meet the T byte / s data throughput requirements of the gigabit era. For standard DRAM, the data read from the unit must go through ...

AI Technical Summary

Problems solved by technology

When the random access memory based on thyristor is working, in order to keep the data, the storage unit needs to periodically activate WL for refresh operation, but like other dynamic memories, it cannot independently perform read and refresh operations through two ports

At the same time, this device is based on SOI substrate, which also has the problems of high cost and complicated circuit design.

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