Deconvolution interweave machine and method realized based on FPGA

Abstract

The invention discloses a deconvolution interleaver based on FPGA and a deconvolution interleaving method. The deconvolution interleaver comprises two dual-port RAMs, two read-write address generators, and a controller, wherein the dual-port RAM has the memory deepness of power of 2,and each of the dual-port RAMs is used in a plurality of shift registers with continuous branch; each of the read-write address generators is connected with a dual-port RAM; the controller is respectively connected with the dual-port RAMs and the read-write address generators, outputs a selecting and controlling signal, and selects one of the read-write address generators to produce the output of read address and write address. The controller also outputs a selecting signal to select the dual-port RAM corresponding to the read address and write address, writes the input data in the memory space corresponding to the read address in the dual-port RAM, or reads and outputs the data in the memory space corresponding to the read address in the dual-port RAM. The invention has the characters of high utility rate of memory space and fast working speed.

Description

technical field [0001] The invention relates to deconvolution interleaving technology, in particular to a deconvolution interleaver and deconvolution interleaving method realized based on FPGA. Background technique [0002] In communication systems, the general role of channel coding is to correct random errors that occur in the channel. However, channel error correction coding often needs to be combined with data interleaving technology in practical applications. This is because most channel errors are sudden, that is, when an error occurs, it often has a strong correlation, and even a continuous piece of data is wrong. At the same time, due to the concentration of errors, the error correction capability of the error correction code may be exceeded, so a data interleaver is added at the sending end, and a deinterleaver is added at the receiving end to disperse the burst errors of the channel to facilitate error correction. Here, adding an interleaver and a deinterleaver to...

AI Technical Summary

Problems solved by technology

[0007] 1. When implemented in an FPGA (Field Programmable Gate Array, Field Programmable Gate Array) logic device, since the FPGA only supports storage memory blocks (registers) with a power-of-two depth, if FIFO is used to implement each branch storage unit, Then the FIFO storage space required by each branch is 256, 256, 256, 256, 128, 128, 128, 128, 64, 64, 32 and 0 bytes in sequence, occupying a total of 1696 bytes of storage space. Therefore, the actual use of The storage space is 1122 bytes, and the utilization efficiency of the storage space is: 1122/1696=66%, so the utilization efficiency of the storage space is low

[0008] 2. The aforementioned design consumes a lo

Images