Memory controller

Abstract

The invention provides a memory controller. The memory controller includes a ring oscillator to generate and to output at least one oscillation clock, an oscillation counter to count the output oscillation clocks, a sampler to receive the reference clock so as to sample oscillation clocks count values during a period of the reference clock, and a phase value output unit to output the sampled oscillation clock count values as a phase value of the reference clock. Thereby, the memory controller can detect the phase value using only two periods of the reference clock, and reduce the initial operation time of a system.

Description

technical field [0001] The present application relates generally to a memory controller, and more particularly, to a memory controller that detects the phase of an input clock. Background technique [0002] A memory controller generally includes a phase detector, a delay controller, and a delay processor, and controls double data rate (DDR). An example of a memory controller is disclosed in Korean Patent Publication No. 2006-83011. [0003] The phase detector includes a delay line having a plurality of delay elements connected in series, each delay element being a delay minimum unit, two delay elements and two flip-flops generating a first phase signal phase1 and a second phase signal phase2 for detecting Phase of the reference clock. The phase detector performs two functions: receiving a reference clock for detecting the phase of the reference clock, and detecting the phase of the reference clock through the delay line for detecting how many delay elements the reference c...

AI Technical Summary

Problems solved by technology

[0005] However, due to the delay line of the phase detector, this conventional technique takes a long time from the initial start-up of the system to phase lock

Because it takes a long time to detect the phase value of the reference clock, the system startup time increases

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