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Delta sigma-type AD converter, class-D amplifier, and DC-DC converter

A technology of converters and subtractors, applied in amplifiers, amplifiers with semiconductor devices/discharge tubes, analog conversion, etc., can solve the problems of increasing costs

Inactive Publication Date: 2008-09-10
YAMAHA CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Then, as a result of increasing the sampling frequency, an operational amplifier capable of high-speed response over a wide range is required as an operational amplifier used in the integrator, which increases the cost

Method used

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  • Delta sigma-type AD converter, class-D amplifier, and DC-DC converter
  • Delta sigma-type AD converter, class-D amplifier, and DC-DC converter
  • Delta sigma-type AD converter, class-D amplifier, and DC-DC converter

Examples

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no. 1 example

[0029] The first embodiment: an embodiment of realizing a ΔΣ-type AD converter.

[0030] FIG. 1 shows a ΔΣ-type AD converter according to an embodiment of the present invention. A subtractor 18 (differential amplifier) ​​subtracts the analog input signal and the feedback signal, thereby outputting a signal proportional to the difference between the signals. The integrator 20 is configured by using an operational amplifier, and the signal output from the subtractor 18 is analog-integrated. The comparator 22 binarizes the signal output from the integrator 20 by comparing with a predetermined threshold value. The counter 24 counts the clock signal of a predetermined frequency, thereby measuring the respective pulse widths of the output signal from the comparator 22 . The data output from the counter 24 is decimated to a predetermined sampling rate by the decimation filter 28 via the loop filter 26 for the purpose of phase compensation and gain adjustment. The data output from ...

no. 2 example

[0038] Second embodiment: An embodiment for implementing a class D amplifier.

[0039] Fig. 6 shows a class D amplifier according to an embodiment of the present invention. A circuit 52 surrounded by a chain line forms a ΔΣ-type AD converter of the present invention. In this AD converter 52, those same elements as those shown in FIG. 1 are assigned the same reference numerals. The subtractor 54 subtracts the digital audio input data and the digital feedback data output from the AD converter 52 . The difference data output from the subtractor 54 is input to the PWM circuit 58 through the loop filter 52 for compensating the phase of the entire loop of the class D amplifier and adjusting the loop gain. The PWM circuit 58 outputs a PWM signal of a predetermined period having a duty ratio responsive to the input difference data. By the PWM signal, the switching element of the switching circuit 60 (class D output stage) is activated or deactivated. The signal output from the swi...

no. 3 example

[0045] Third embodiment: an embodiment for realizing a DC-DC converter.

[0046] Fig. 11 shows a DC-DC converter according to an embodiment of the present invention. This DC-DC converter has the structure of the aforementioned class D amplifier shown in FIG. 6, in which digital target value data (target value of DC output voltage) is input instead of digital audio input data, and in which an arbitrary load instead of the speaker 64 is connected. 70. The same reference numerals are assigned to those elements that are the same as those shown in FIG. 6 . The circuit operates in the same manner as the circuit shown in FIG. 6 . When the voltage output from the LC low-pass filter 62 fluctuates as a result of a change in the load 70 , the fluctuation is suppressed by the negative feedback loop composed of the AD converter 52 . In particular, the dynamic range of the AD converter 52 is improved by the resolving power of the PWM circuit 30, and thus a high dynamic range can be obtai...

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Abstract

A GBP-type AD converter includes a subtractor which receives an analogue input signal and a feedback signal and which outputs a signal pertaining to a difference between the signals, an integrator which integrates a signal output from the subtractor, a comparator which binarizes a signal output from the integrator by comparing with a predetermined threshold value, a counter which measures respective pulse widths of a signal output from the comparator, and a PWM circuit which outputs a pulse signal of a predetermined period having a duty cycle responsive to a count value output from the counter and which feeds back the pulse signal as the feedback signal to the subtractor. The counter measures the respective pulse widths in each PWM frame period in synchronism with the PWM circuit, and the PWM circuit feeds back to the subtractor a pulse signal whose duty cycle is set in accordance with a value of the measured pulse width in a next PWM frame. A count value output from the counter is extracted as a converted digital output value.

Description

technical field [0001] The present invention relates to a ΔΣ-type AD converter configured such that a high dynamic range is exhibited when the ΔΣ-modulation sampling frequency is suppressed to a relatively low level. The invention also provides a class D amplifier and a DC-DC converter using the ΔΣ AD converter. Background technique [0002] FIG. 2 shows a related art ΔΣ-type AD converter. The subtractor 10 subtracts the analog input signal and the feedback signal. Integrator 14 integrates the signal output from subtractor 10 . The quantizer 16 compares the signal output from the integrator 14 with a predetermined threshold value, thereby binarizing the signal. The signal output from the quantizer 16 is a 1-bit digital signal that takes the value "1" or "0" in the sampling interval unit of the ΔΣ modulation, and the 1-bit digital signal is subjected to analog-to-digital conversion, and the conversion result is output . This 1-bit signal is subjected to a single-sample d...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M3/02H03M1/52H03F3/217H02M3/155
CPCH03M3/344H02M3/157H03M3/424H03M3/50H03F3/2175H03M3/02H03F3/217H02M3/28
Inventor 森岛守人
Owner YAMAHA CORP