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Method for multithread sharing multi-core processor secondary buffer memory based on data classification

A multi-core processor and data division technology, applied in the field of multi-core and multi-thread, can solve problems such as unreachable, achieve the effect of improving performance, reducing stimulus-response cycle, and shortening running time

Inactive Publication Date: 2008-10-15
ZHEJIANG UNIV
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  • Application Information

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Problems solved by technology

However, past research mainly improved the real-time performance of the system from the indirect level such as the operating system, and could not touch the fundamental problem - real-time tasks

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  • Method for multithread sharing multi-core processor secondary buffer memory based on data classification
  • Method for multithread sharing multi-core processor secondary buffer memory based on data classification
  • Method for multithread sharing multi-core processor secondary buffer memory based on data classification

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Embodiment Construction

[0025] The present invention is a kind of method based on multi-thread sharing multi-core processor secondary cache of data division, combined below figure 1 Describe its specific implementation process.

[0026] 1) Data-based multi-thread division:

[0027] The program is mainly composed of two parts, the control of the program flow and the operation of the data. For a single task, the control of the program flow cannot be further divided, but its data operation part can be decomposed, and the execution time occupied by the data operation part is generally much longer than that of the flow control part. picture figure 2 (a) Such program code is relatively common in program coding. But with a single-core architecture, parallelism, even if possible, cannot be exploited. But in multi-core architecture, the situation is different. figure 2 (b) shows that the original program can be decomposed into two threads to perform calculations respectively. According to this divisio...

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Abstract

The invention discloses a method for multi-thread sharing multi-core processor secondary buffer memory, which is based on data division. The method of the invention combines the characteristic of the secondary buffer memory on the multi-core processor, carries out the multi-thread division of the programs which are based on the data, and designs a thread distribution arithmetic based on the secondary buffer memory sharing in the operation system so as to provide the supporting to the running of the task after division. The method of the invention realizes the multi-thread sharing of the secondary buffer memory on the multi-core processor and greatly improves the performance of real-time task of the system, thus reducing the excitation-response period of the system. The method of the invention realizes the multi-thread sharing of the secondary buffer memory on the multi-core processor, and greatly improves the performance of the real-time task of the system, thus reducing the excitation-response period of the system; the multi-spread can run on the system at the same time and greatly shortens the running time of the whole task.

Description

technical field [0001] The invention relates to the technical field of multi-core and multi-threading, in particular to a method for sharing a second-level cache of a multi-core processor with multiple threads based on data division. Background technique [0002] With the development of integrated circuit technology, the performance improvement of the processor can no longer be counted on the increase of the main frequency. In order to make the performance of the microprocessor continue to advance according to Moore's law, so that the processor can meet the needs of computing development, it is necessary to study a new micro-architecture And new computing models, so the single-chip multi-processor (ChipMulti-processors, referred to as CMP) architecture, which is commonly referred to as multi-core, has become a hot spot in academia and industry, and has become the mainstream in the server and desktop fields. . [0003] The proposal of each new hardware architecture must coop...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F12/08G06F9/46G06F9/48G06F12/0893
Inventor 陈天洲胡威施青松严力科谢斌黄江伟章铁飞冯德贵项凌祥蒋冠军
Owner ZHEJIANG UNIV
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