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Method for forming fine pattern of semiconductor device

一种精细图案、半导体的技术,应用在半导体/固态器件制造、电气元件、电路等方向,能够解决覆盖对准不良、无法获得图案等问题,达到改善覆盖对准不良的效果

Inactive Publication Date: 2008-12-10
SK HYNIX INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

As a result, the double patterning technique cannot obtain the desired pattern
During the alignment process, coverage misregistration occurs

Method used

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  • Method for forming fine pattern of semiconductor device
  • Method for forming fine pattern of semiconductor device
  • Method for forming fine pattern of semiconductor device

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Experimental program
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Embodiment Construction

[0025] Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

[0026] To prevent overlay and misalignment, two methods have been developed: i) Double Exposure Etching Technology (DEET) and ii) Spacer Patterning Technology (SPT), which have been used in the fabrication process of semiconductor devices.

[0027] DEET involves forming first patterns with a line width twice that of the desired pattern, and forming a second pattern with the same line width between the first patterns. More specifically, DEET includes a) a positive approach and b) a negative approach.

[0028] As shown in FIG. 1 , in the positive type method, an underlayer 3 , a first mask film 5 , a second mask film 7 and a first positive photoresist pattern 8 are formed over a semiconductor substrate 1 . A second mask pattern 7-1 is formed using the first positive photoresist pattern 8 as an etch stop mask. A second positive photoresist pattern 9 is formed bet...

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PUM

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Abstract

A method for forming a fine pattern of a semiconductor device comprises forming a deposition pattern including first, second, and third mask patterns over a semiconductor substrate having an underlying layer, side-etching the second mask pattern with the third mask pattern as an etching barrier mask, removing the third mask pattern, forming a spin-on-carbon layer that exposes the upper portion of the second mask pattern, performing an etching process to expose the underlying layer with the spin-on-carbon layer as an etching barrier mask, and removing the spin-on-carbon layer.

Description

technical field [0001] The present invention generally relates to a method of forming a fine pattern of a semiconductor device. Background technique [0002] Due to the spread of information media such as computers, semiconductor device technology has been rapidly developed. Semiconductor devices are required to operate at high speed and have high memory capacity. As a result, semiconductor device manufacturing techniques are required to manufacture high-capacity memory elements with higher integration, reliability, and data access characteristics. [0003] In order to increase the integration of devices, photolithography has been developed to form fine patterns. Photolithography techniques include exposure techniques using chemically amplified deep ultraviolet (DUV) light sources such as ArF (193nm) and VUV (157nm), and techniques of developing photoresists suitable for exposure light sources. [0004] As semiconductor devices become smaller, it is important to control t...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/00H01L21/027H01L21/3213H01L21/311
CPCH01L21/0332H01L21/0337H01L21/0338H01L21/32139H01L21/02134H01L21/0217H01L21/02164H01L21/0214H01L21/02137H01L21/02115H01L21/022H01L21/02107H01L21/0274H01L21/31608H01L21/3185H01L21/3143H01L21/3146
Inventor 李基领卜喆圭潘槿道
Owner SK HYNIX INC
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