Counter circuit structure and electronic device using the same

Abstract

The invention discloses a circuit structure for a counter and an electronic device applied to the circuit structure for the counter. The circuit structure for the counter and the electronic device are suitable for calculating the periodicity of one digital signal relative to one frequency signal, wherein the signal modal of the digital signal is a nonreturn-to-zero code. The circuit structure for the counter comprises a first counter module and a second counter module, wherein the first counter module receives the digital signal and the frequency signal; when the digital signal is in a high level, the first counter module calculates the periodicity of the signal width of the digital signal relative to the frequency signal; the second counter module receives an inverted signal of the digital signal and the frequency signal; and when the inverted signal of the digital signal is in a high level, the second counter module calculates the periodicity of the signal width of the inverted signal of the digital signal relative to the frequency signal. The counter circuit has a simplified structure, reduces the use amount of the components of a logic circuit, further reduces the occupied area of the circuit structure, lowers the power consumption, and facilitates the application of the integrated circuit.

Description

technical field [0001] The invention relates to a counter circuit structure, in particular to a counter circuit structure suitable for calculating the signal width of a digital signal, and an electronic device for its application. Background technique [0002] In digital logic circuits, the circuit structure of a counter (Timer counter) is a circuit type that is widely used. Counter circuits are often used in decoding systems as signal width calculators for digital signals. Please refer to FIGS. 1, 2, and 3. FIG. 1 and FIG. 2 are schematic diagrams of a system structure of a counter circuit structure 1 in the prior art, and FIG. 2 is a schematic diagram of a circuit structure of the counter module 10 in FIG. 1 . image 3 It is a timing diagram of the digital signal R and the inverted digital signal R'. The counter circuit structure 1 shown in Figs. 1 and 2 is suitable for calculating the signal width of the digital signal R. [0003] The signal type of the digital signal R...

AI Technical Summary

Problems solved by technology

[0007] The above-mentioned prior art counter circuit structure 1 must be realized by using one counter module 10 and two buffer modules 12, 14, therefore, when the number of bits increases, the number of logic circuit components used therein will increase three times with the number of bits , causing the area and power consumption of the integrated circuit chip occupied by the counter circuit structure 1 to increase at the same time

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