Flash memory and manufacturing method therefor

Abstract

Disclosed is a flash memory, comprising a substrate, a stack structure arranged on the substrate, a source electrode, a drain electrode and a source terminal spacing layer; wherein the stack structure is composed of a tunnel oxide layer, a charge storage layer arranged on the tunnel oxide layer, an inter-gate medium layer arranged on the charge storage layer and a control grid arranged on the inter-gate medium layer. The source electrode and the drain electrode are arranged in the substrate respectively at two sides of the charge storage layer. The source terminal spacing layer is arranged on one side wall of the stack structure, which is close to the source electrode, so as to prevent the parts of the tunnel oxide layer and the inter-gate medium layer, which are close to the source electrode, from being oxidized again, which leads to the increase of the thickness.

Description

technical field [0001] The present invention relates to a non-volatile memory and a manufacturing method thereof, and more particularly, to a flash memory having an asymmetric spacer layer structure and a manufacturing method thereof. Background technique [0002] A typical flash memory uses doped polysilicon to form a charge storage layer and a control gate. When the memory is programmed, appropriate programming voltages are applied to the source, drain and control gate, respectively, and electrons will flow from the source to the drain through a channel. During this process, some electrons will pass through the tunneling oxide layer under the polysilicon charge storage layer, enter and be uniformly distributed in the entire polysilicon charge storage layer, and the electrons will pass through the tunneling oxide layer. The phenomenon of entering the polysilicon charge storage layer is called the tunneling effect. The tunneling effect can be divided into two cases, one is...

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Problems solved by technology

[0006] However, if Figure 1B As shown, after the annealing process 116, whether it is the edge thickness t of the tunnel oxide layer 102 or the inter-gate dielectric layer 106 edge both become thicker than their central thickness t center Thick, so it is not conducive to the control of the gate coupling ratio (gate coupling ratio, GCR) between the charge storage layer and the control gate, which affects the operating voltage and device speed

Moreover, when the flash memory performs an erase operation, the area between the tunnel oxide layer 102 and the channel (that is, the area between the source electrode 118a and the drain electrode 118b) is related, so when the edge of the tunnel oxide layer 102 When thickened, it will not be conducive to the erasing operation of the component

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