Gate layer manufacturing method, semiconductor device manufacturing method and semiconductor construction

Abstract

A manufacturing method of a grid layer comprises the steps of providing a semiconductor substrate with a grid electrode insulating layer; forming a first polycrystalline silicon layer on the semiconductor substrate; forming a second polycrystalline silicon layer with randomly distributed crystal grains; and carrying out ion implantation doping to the second and the first polycrystalline silicon layers. The invention also provides a manufacturing method of a semiconductor device, and a semiconductor structure. The method can prevent or reduce doping ions from entering into or passing through the grid electrode insulating layer when carrying out ion implantation doping to the grid electrode layers.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a manufacturing method of a gate layer, a manufacturing method of a semiconductor device and a semiconductor structure. Background technique [0002] With the continuous improvement of semiconductor manufacturing technology, the integration level is getting higher and higher, and the critical dimension of the gate representing the level of semiconductor manufacturing technology is getting smaller and smaller; in metal oxide semiconductor transistors, polysilicon is generally used as the material for manufacturing the gate , Moreover, in order to reduce power consumption and improve response speed, polysilicon is often doped to form doped polysilicon to reduce the resistance of the gate, for example, for the polysilicon gate of an N-type metal oxide semiconductor transistor (NMOS), N-type impurities are doped, and for the polysilicon gate of a P-type metal oxid...

AI Technical Summary

Problems solved by technology

[0009] In the process of using doped polysilicon to form the gate, the energy and energy of ion implantation during doping are very large, the implanted energy can reach 5KeV to 15KeV, and the dose can reach 2×10 15 atom / cm 2 up to 5×10 15 atom / cm 2 , the implanted ions will enter or penetrate the gate insulating layer, causing electrical problems such as threshold voltage drift and leakage current increase of the metal oxide semiconductor device formed.

Images