Semiconductor device and method of processing the same

Abstract

Provided is a semiconductor wafer and manufacturing method thereof. In the prior case of the super junction structure formed by repeatedly performing formation of a multiple epitaxial layers and ion implantation in the thickness direction of the semiconductor wafer, the pn junction surfaces become undulate practically. Thus, there is a problem that the depletion layer hardly spread uniformly in a precise sense. In a method of using slope ion injection to form a partly column shape semi-conductor layer, the ion is also needed to injected below the grooves for uniform impurity distribution in the wafer perpendicular direction, thereby a problem of increasing invalid regions exists. In the semiconductor wafer, formation and etching of an n type epitaxial layer and formation and etching of a p type epitaxial layer are alternately performed for at least three times, so that all semiconductor layers are formed of epitaxial layers on a semiconductor substrate. Thereby, the respective semiconductor layers can be formed to have reduced widths. Thus, if a required breakdown voltage is the same, dopant concentrations of the respective semiconductor layers can be increased and a resistance value of the wafer can be reduced. In addition, a space portion remaining in the end is buried with an insulating layer, so that a defect can be avoided in a junction surface of the epitaxial layers.

Description

technical field [0001] The present invention relates to a method of manufacturing a semiconductor wafer, and more particularly, to a method of manufacturing a semiconductor wafer capable of shortening the manufacturing process of a semiconductor wafer that realizes high breakdown voltage and low on-resistance and improves characteristics. Background technique [0002] As a silicon semiconductor wafer capable of realizing high withstand voltage and low on-resistance, there is known a wafer structure in which a p-type semiconductor region and an n-type semiconductor region are arranged in a columnar shape, and a plurality of pn junctions (such as Refer to Patent Document 1). [0003] In these wafer structures, by selecting desired values ​​for the impurity concentration and width of the p-type semiconductor region and the n-type semiconductor region, it is possible to realize a high breakdown voltage using the pn junction when a reverse voltage is applied. Such a structure wi...

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Problems solved by technology

Therefore, it is difficult to configure a large number of superstructure structures

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