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Semiconductor encapsulation stacking combined construct for protecting welding spot between external pins

A technology of packaging stacking and external pins, which is used in semiconductor devices, semiconductor/solid-state device components, electric solid-state devices, etc., and can solve the problems of inconvenience, general products without suitable structure, and solder joint fracture

Inactive Publication Date: 2010-09-29
POWERTECH TECHNOLOGY INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Therefore, part of the solder joints of the second pins 123 bear excessive concentrated stress, especially the side edge pins of the second pins 123, there will be a problem of solder joint fracture
[0005] It can be seen that the above-mentioned existing semiconductor package stacking combination structure obviously still has inconvenience and defects in structure and use, and needs to be further improved urgently.
In order to solve the above-mentioned problems, the relevant manufacturers have tried their best to find a solution, but no suitable design has been developed for a long time, and the general products do not have a suitable structure to solve the above-mentioned problems. Urgent problem

Method used

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  • Semiconductor encapsulation stacking combined construct for protecting welding spot between external pins
  • Semiconductor encapsulation stacking combined construct for protecting welding spot between external pins
  • Semiconductor encapsulation stacking combined construct for protecting welding spot between external pins

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Embodiment Construction

[0048] In order to further illustrate the technical means and effects that the present invention takes to achieve the intended purpose of the invention, below in conjunction with the accompanying drawings and preferred embodiments, the structure of the semiconductor package stacking combination for protecting the solder joints between the outer pins proposed according to the present invention will be described below. Specific embodiments, structures, features and effects thereof are described in detail below.

[0049] The aforementioned and other technical contents, features and effects of the present invention will be clearly presented in the following detailed description of preferred embodiments with reference to the drawings. Through the description of the specific implementation mode, when the technical means and functions adopted by the present invention to achieve the predetermined purpose can be obtained a deeper and more specific understanding, but the accompanying dra...

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Abstract

The invention relates to a semiconductor package stacking combination structure for protecting soldered joints among outer leads. The structure mainly comprises a plurality of mutually stacked semiconductor packaging parts and non-conducting gluing. Each semiconductor packaging part comprises at least one wafer, a plurality of outer leads of a lead frame and a colloid, and the outer leads are exposed at the side edges of the colloid, wherein, end faces of a plurality of outer leads of an upper-layer semiconductor packaging part are soldered on one segment of the corresponding outer leads of alower-layer semiconductor packaging part. The non-conducting gluing is formed on the end faces of the outer leads of the upper-layer semiconductor packaging part along the side edges of the colloid of the lower-layer semiconductor packaging part so as to partially or fully clad the soldered joints among the outer leads of the upper-layer semiconductor packaging part and the lower-layer semiconductor packaging part. The semiconductor package stacking combination structure can help achieve the stress dispersion of the soldered joints among the outer leads and avoid short circuits.

Description

technical field [0001] The invention relates to a leadframe-based semiconductor package stacking combination structure (leadframe-based POP device), in particular to a kind of structure that can avoid solder joint fracture caused by the difference in thermal expansion coefficient between the sealant and the leadframe, and can also prevent electrical contact between pins. In addition, it can absorb the stress of the difference in the thermal expansion coefficient of the sealing body and the lead frame acting on the solder joints between the outer pins, and protect the solder joints between the outer pins. The semiconductor package stacking combination structure. Background technique [0002] In recent years, high-tech electronic products have continuously launched electronic products that are more user-friendly and have better functions, resulting in a trend of lighter, thinner, shorter and smaller products. Therefore, a combination of semiconductor components is to stack mul...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L25/00H01L23/488H01L23/28
CPCH01L2224/32245H01L2224/48091H01L2224/4826H01L2224/73215
Inventor 范文正陈正斌
Owner POWERTECH TECHNOLOGY INC