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Semiconductor device and method of manufacturing the same

A device manufacturing method and semiconductor technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical solid-state devices, etc., can solve the problems of NAND-type EEPROM electrical reliability reduction and other issues

Inactive Publication Date: 2004-06-09
KK TOSHIBA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This corner is prone to electric field concentration, and similar to the above, there is a danger of an electrical short circuit between the word line 123WL and the well region 101, which reduces the electrical reliability of the NAND type EEPROM.

Method used

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  • Semiconductor device and method of manufacturing the same
  • Semiconductor device and method of manufacturing the same
  • Semiconductor device and method of manufacturing the same

Examples

Experimental program
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Effect test

no. 1 Embodiment

[0050] [Semiconductor device structure with non-volatile memory circuit]

[0051] The first embodiment of the present invention is to describe a semiconductor device equipped with a NAND-type EEPROM. Here, the term “semiconductor device” is used in the sense that it includes at least a semiconductor memory with only NAND-type EEPROM function, and a semiconductor device that includes logic circuits and other circuits on the same substrate in addition to NAND-type EEPROM.

[0052] Such as Figure 1 to Figure 3 As shown, the NAND-type EEPROM according to the first embodiment of the present invention includes memory cells M arranged in rows and columns on a semiconductor substrate 1 (or well region 2), the memory cells M having a floating electrode (floating gate electrode) 5 memory cells MA; between the memory cells M along the gate width direction (the direction in which the word line extends), there is a first trench 30 provided in the depth direction from the surface of the semico...

no. 2 Embodiment

[0113] The second embodiment of the present invention is to describe an example of replacing the cross-sectional shape of the second groove 20 in a semiconductor device provided with the NAND-type nonvolatile memory circuit of the first embodiment of the present invention.

[0114] A semiconductor device having a NAND-type nonvolatile memory circuit according to the second embodiment of the present invention, such as Picture 12 As shown, the isolation filling material 31 of the element isolation region 3 is provided with a second groove 21 having a U-shaped cross-sectional shape. That is, as with the second groove 20 of the first embodiment of the present invention, the groove width of the second groove 21 facing the surface portion in the grid width direction, and the groove width forming the depth portion is small. Therefore, the separation distances L1 and L2 between the sidewall of the second groove 21, particularly the bottom of the well region 2 and the well region 2 can be...

no. 3 Embodiment

[0119] The third embodiment of the present invention is to describe an example of replacing the cross-sectional shape of the second groove 20 in a semiconductor device equipped with a NAND-type nonvolatile memory circuit of the first embodiment of the present invention.

[0120] A semiconductor device equipped with a NAND-type nonvolatile memory circuit according to the third embodiment of the present invention, such as Figure 13 As shown, the isolation filling material 31 of the element isolation region 3 is provided with a second groove 22 having an inverted mesa-shaped cross-sectional shape. That is, as with the second groove 20 of the first embodiment of the present invention, the groove width of the second groove 22 in the grid width direction to the surface portion and the groove width forming the depth portion is small. Therefore, the separation distances L1 and L2 between the sidewalls of the second groove 22, particularly the bottom of the well region 2 and the well regi...

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Abstract

A semiconductor device having a high reliability nonvolatile memory circuit that can avoid the word line to substrate short, and its manufacturing method are provided. The semiconductor device with a nonvolatile memory circuit consists of: a device isolation area 3 that has a first trench 30 and isolation filler 31 filled in the trench; a second trench 20 that is formed between the floating electrodes 5 of the memory cells M adjacent to each other along the gate width direction, and is narrow on the bottom thereof; and word line (WL) 7 that has a part buried in the second trench 20.

Description

Technical field [0001] The present invention relates to a semiconductor device and a manufacturing method thereof, and in particular to a semiconductor device provided with a non-volatile memory circuit and a manufacturing method thereof. Background technique [0002] Figure 21 Shows the cross-sectional structure of a NAND-type electrically erasable program read-only memory (hereinafter referred to as EEPROM). Figure 21 It is a cross-sectional view when the memory cell array is cut along the word line direction. The NAND type EEPROM includes a semiconductor substrate 100 made of a silicon single crystal, memory cells M arranged in regular rows and columns on the main surface of the semiconductor substrate 100, and element isolation regions 110 provided between the memory cells M. [0003] The memory cell M is composed of one transistor having a floating electrode (floating gate electrode) 121. That is, the memory cell M includes a gate insulating film 120 on the surface of the...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/76H01L21/3213H01L21/8247H01L27/115H01L29/788H01L29/792
CPCH01L27/11524H01L27/11521H01L27/115H10B41/35H10B69/00H10B41/30
Inventor 井口直石田胜广角田弘昭饭塚裕久间博顕森诚一
Owner KK TOSHIBA
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