Method for source/drain injection in semiconductor device production
A semiconductor, source-drain technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the problems of high photolithography cost, difficult polysilicon sidewall manufacturing process, high cost of polycrystalline etching, etc., to achieve cost reduction , Avoid the effect that etching is difficult and the production requires precision
Inactive Publication Date: 2009-05-13
SHANGHAI HUA HONG NEC ELECTRONICS
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[0002] In the existing manufacturing process of semiconductor devices, four photolithographic layers are usually required to complete the four layers of N-type source and drain regions, N-type lightly doped drain regions, P-type source and drain regions, and P-type lightly doped drain regions. Ion implantation in the area, so the cost of lithography is relatively high
However, when polysilicon is used to make polysilicon sidewalls and used as barrier layers in shallowly doped regions, the manufacturing process of polysilicon sidewalls is relatively difficult, and the cost of polysilicon etching is high.
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[0029] In the method of the present invention, the substrate can be a general-purpose semiconductor silicon chip in the industry at present, and an N region and a P region are defined earlier on the substrate to form an isolation oxide region and a polysilicon gate (see figure 2 ) After that, it is completed through eight major steps, figure 1 It is an implementation flowchart of the method of the present invention:
[0030] (1) First deposit silicon nitride on the substrate surface of the N region and the P region (see image 3 ), used as a barrier layer. The thickness of this layer of silicon nitride is about 80-200 angstroms, preferably 100 angstroms;
[0031] (2) Finally, silicon oxide is deposited on the entire substrate, which can be prepared by a low-pressure chemical vapor deposition process, and the deposited silicon oxide should cover the steps formed by the entire polysilicon gate (see Figure 4 ), and then use an isotropic etching process (such as a wet etching...
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The invention discloses a source-drain implantation method use in the preparation of a semiconductor component. The method comprises the following steps: depositing silicon nitride; depositing silicon oxide, and etching the silicon oxide to form a silicon oxide lateral wall; exposing an N region by means of photoetching of an N region photoetching mask and then carrying out N source-drain heavy doping ion implantation; removing the silicon oxide lateral wall of the N region, and then carrying out N source-drain light implantation; removing the photosensitive resist; exposing a P region by means of photoetching of a P region photoetching mask and then carrying out P region source-drain heavy doping ion implantation; removing the silicon oxide lateral wall of the P region, and then carrying out P source-drain light implantation; and removing the photosensitive resist and finishing the source-drain implantation process. The method only uses two photoetching masks to finish the source-drain implantation; and compared with the prior art, the preparation cost is reduced; and the method can be widely used for semiconductor component preparation.
Description
technical field [0001] The invention relates to a method for source-drain implantation in the preparation of semiconductor devices. Background technique [0002] In the existing manufacturing process of semiconductor devices, four photolithographic layers are usually required to complete the four layers of N-type source and drain regions, N-type lightly doped drain regions, P-type source and drain regions, and P-type lightly doped drain regions. Ion implantation in the area, so the cost of lithography is relatively high. However, when the polysilicon sidewall is made of polysilicon and used as a barrier layer in the shallowly doped region, the manufacturing process of the polysilicon sidewall is relatively difficult, and the cost of polysilicon etching is high. Contents of the invention [0003] The technical problem to be solved by the present invention is to provide a method for source-drain implantation in the preparation of semiconductor devices, which can reduce the ...
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IPC IPC(8): H01L21/8238H01L21/336H01L21/266
Inventor 曾金川
Owner SHANGHAI HUA HONG NEC ELECTRONICS