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Apparatus and method for improving drive strength, leakage and stability of deep submicron MOS transistors and memory cells

A MOS transistor and transistor technology, applied in the direction of transistors, information storage, static memory, etc., can solve the problems of increasing the dead zone and reducing the beneficial characteristics of the device

Inactive Publication Date: 2013-08-14
SEMI SOLUTIONS LLC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, these approaches result in a significant increase in dead zone, reduce other beneficial characteristics of the device, and require manufacturing process changes, among other limitations

Method used

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  • Apparatus and method for improving drive strength, leakage and stability of deep submicron MOS transistors and memory cells
  • Apparatus and method for improving drive strength, leakage and stability of deep submicron MOS transistors and memory cells
  • Apparatus and method for improving drive strength, leakage and stability of deep submicron MOS transistors and memory cells

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Embodiment Construction

[0046] The core of the disclosed invention lies in adding a circuit for increasing the driving current in the on state and reducing the leakage current in the off state to the NMOS transistor. In particular, this is achieved by implementing a control circuit between the gate of the transistor and the substrate. The control circuit can be as simple as a resistor, or it can include one or more diodes. In particular, the circuit forces the high threshold voltage V of the NMOS transistor in the off-state TH and the on-state of the NMOS transistor in the low V TH . The following is a detailed description of the disclosed invention.

[0047] figure 2 Shown is an exemplary, non-limiting schematic diagram of a circuit 200 in accordance with the disclosed invention. The control circuit Zc260 is connected to an NMOS transistor including a substrate 220 , a gate 230 , a drain 240 and a source 250 . The control circuit is connected between the gate 230 and the substrate 220 . Accor...

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Abstract

An apparatus and method for manufacturing metal-oxide semiconductor (MOS) transistors that are operable at voltages below 1.5V, which MOS transistors are area efficient, and where the drive strength and leakage current of the MOS transistors is improved. The invention uses a dynamic threshold voltage control scheme that does not require a change to existing MOS technology processes. The invention provides a technique that controls the threshold voltage of the transistor. In the OFF state, the threshold voltage of the transistor is set high, keeping the transistor leakage to a small value. In the ON state, the threshold voltage is set to a low value, resulting in increased drive strength. The invention is particularly useful in MOS technology for both bulk and silicon on insulator (SOI) CMOS. The invention is further useful for SRAM, DRAM, NVM devices and other memory cells.

Description

[0001] Cross References to Related Applications [0002] This application claims U.S. Patent Application 11 / 027,181, filed December 29, 2004, U.S. Patent Application 11 / 029,542, filed January 4, 2005, U.S. Patent Application 11 / 110,457, filed April 19, 2005, and 2005 Priority to U.S. Provisional Patent Application Serial No. 60 / 717,769, filed September 19, 2009, the contents of each application are hereby incorporated by reference in their entirety. technical field [0003] The present invention mainly relates to MOS (Metal Oxide Semiconductor) based transistors and memory cells. More particularly, the present invention relates to a deep submicron MOS transistor with improved drive capability, leakage current, and stability, and a memory cell using the deep submicron MOS transistor. Background technique [0004] As the minimum feature size shrinks below 100nm and the supply voltage decreases below 1.0V, conventional complementary metal-oxide-semiconductor (CMOS) technology ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/76
CPCG11C16/0408G11C7/1057H01L27/1052H01L27/0629G11C7/1084H01L29/783G11C11/412G11C7/1078H01L27/105H01L21/8239G11C11/404G11C7/1051H10B10/10H10B12/10
Inventor 阿肖科·卡普尔罗伯特·斯特兰鲁文·马可
Owner SEMI SOLUTIONS LLC