Multi-chip stacking structure and preparation thereof

Abstract

The invention discloses a multichip stacking structure and a method for manufacturing the same. The multichip stacking structure comprises a first chip set which is provided with a plurality of first chips and is connected with a chip bearing piece in a stepped mode; the first chip of the topmost layer of the first chip set is connected with a second chip so that the first chip and the second chip are in electric connection with the chip bearing piece through a welding wire; adhesive film over wire technology (Film over Wire, FOW) is utilized to stack a third chip alternated with an insulating adhesive film on the first chip and the second chip so that the insulating adhesive film covers part of the welding wire end of the first chip of the topmost layer of the first chip set and at leastone part of the second chip and is in electric connection with the third chip and the chip bearing piece through the welding wire, thereby solving the problem that when the second chip with planar dimension far less than that of the first chip is directly stacked on the first chip in the prior art, the height of the whole structure and the difficulty of wire welding operation are increased.

Description

technical field [0001] The invention relates to a semiconductor structure and its manufacturing method, in particular to a multi-chip stacking structure and its manufacturing method. Background technique [0002] Due to the miniaturization of electronic products and the increase in the demand for high operating speed, in order to improve the performance and capacity of a single semiconductor package structure to meet the needs of miniaturization of electronic products, it has become a trend for the semiconductor package structure to adopt multi-chip modularization (Multichip Module), thus In this way, two or more chips are combined in a single package structure to reduce the volume of the overall circuit structure of electronic products and improve electrical functions. That is, the multi-chip package structure can minimize the limitation of system operation speed by combining two or more chips in a single package structure; in addition, the multi-chip package structure can ...

AI Technical Summary

Problems solved by technology

[0010] However, the above-mentioned method still cannot solve the problem that when the control chip is electrically connected to the chip carrier by the bonding wire, the bonding wire crosses too many memory chips under the control chip, which may easily cause the bonding wire to touch the memory chip and cause a short circuit. problem, and increase the difficulty of welding wire operation; in addition, the length of the welding wire required by this method is too long and the welding arc is too high, which not only increases the manufacturing cost but also easily leads to the problem of wire sweep (wire sweep)

[0011] At the same time, since the aforementioned method needs to add an additional buffer layer during the chip stacking process, the manufacturing cost and steps increase; moreover, due to the addition of the buffer layer, the height of the multi-chip stacking structure cannot be effectively reduced, which is not conducive to Fabrication of thin electronic devices (such as Micro-SD cards)

[0012] Furthermore, in the aforementioned manufacturing techniques, the control chip is stacked on top of the memory chip, not only the height of the stack structure is limited, but also the problem of exposure will easily occur if the arc height of the bonding wire is not well controlled, and the bonding wire is too long It will also lead to a decrease in the quality of the electrical connection, and when the number of stacked layers increases, the probability of delamination at the interface layer will increase and increase the complexity of the process, resulting in more stringent and time-consuming process control

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