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Method for etching bottom layer anti-reflection layer and manufacturing wire laying slot

An anti-reflection layer and etching technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve problems such as affecting the accuracy of wiring trenches, and achieve the effect of slowing down the etching rate and accelerating the etching rate.

Active Publication Date: 2009-06-17
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The invention provides a method for etching the bottom anti-reflection layer and a method for making a wiring groove, which solves the problem in the prior art that a mesa is formed in the process of forming a wiring groove, thereby affecting the accuracy of the wiring groove process

Method used

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  • Method for etching bottom layer anti-reflection layer and manufacturing wire laying slot
  • Method for etching bottom layer anti-reflection layer and manufacturing wire laying slot
  • Method for etching bottom layer anti-reflection layer and manufacturing wire laying slot

Examples

Experimental program
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Embodiment approach

[0026] refer to image 3 As shown, an embodiment of the method for fabricating wiring trenches in the present invention includes the following steps,

[0027] Step s10, providing a semiconductor structure, the semiconductor structure comprising a multilayer structure consisting of a lower insulating layer, an etching stop layer on the lower insulating layer, an upper insulating layer on the etching stop layer, and an anti-reflection layer on the upper insulating layer, the The multilayer structure has a groove, and the bottom antireflection layer is covered in the groove and on the surface of the antireflection layer;

[0028] Step s20, etching the bottom anti-reflection layer on the wafer to remove the bottom anti-reflection layer to expose the anti-reflection layer, wherein the bottom anti-reflection layer on the wafer includes the bottom anti-reflection layer at the center of the wafer and the surrounding The bottom anti-reflection layer of the bottom anti-reflection layer...

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Abstract

A method of etching bottom anti-reflection layers includes steps of adding a magnetic field while etching bottom anti-reflection layers on a wafer, which leads the etching rate of the bottom anti-reflection layer on the edge of the wafer to be faster than that of the bottom anti-reflection layer at the center of the wafer. The invention further discloses a method of manufacturing wiring trenches. The method of etching bottom anti-reflection layers and the method of manufacturing wiring trenches are capable of increasing the precision of wiring trench manufacture.

Description

technical field [0001] The invention relates to a method for etching a bottom anti-reflection layer and making wiring grooves. Background technique [0002] As the integration level of semiconductor elements increases, the line width of semiconductor elements becomes smaller and smaller, and the control of critical dimensions becomes more and more important. In the photolithography process, due to the level difference of the wafer surface, when the photoresist covers the wafer surface, the thickness of the photoresist layer will vary according to the planarization characteristics of the photoresist. When the lithography light travels in the photoresist, the reflected light on the wafer surface and the incident light will form a gain / loss interference phenomenon, thus producing the so-called swing effect. The uneven thickness of the above-mentioned photoresist and the swing effect will both cause adverse effects of critical dimension changes. [0003] Due to the widespread ...

Claims

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Application Information

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IPC IPC(8): H01L21/311H01L21/768
Inventor 周鸣沈满华
Owner SEMICON MFG INT (SHANGHAI) CORP
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