Preparation method for complementary metal oxide semiconductor element with dual metal grid

Abstract

The invention discloses a production method of a CMOS element with bimetal grids. The method comprises: a first conductive transistor and a second conductive transistor are formed respectively on a substrate that is provided with a first active area, a second active area and a shallow trench isolation providing an electric isolation; a metal silicide technology is carried out; an internal dielectric layer is formed on the substrate; a first etching technology is carried out; a part of grid of the first conductive transistor is removed and an opening is formed; and a high-dielectric constant gird dielectric layer of the first conductive transistor is exposed on the bottom of the opening, and a first metal layer is formed in the opening.

Description

Technical field

[0001] The present invention relates to a method for manufacturing a complementary metal-oxide semiconductor (complementary metal-oxide semiconductor, hereinafter referred to as CMOS) device with a dual metal gate, especially a gate last ) A manufacturing method of a CMOS device with a dual metal gate in the process. Background technique

[0002] As the size of CMOS devices continues to shrink, the traditional methods of reducing the gate dielectric layer, such as reducing the thickness of the silicon dioxide layer, to achieve the purpose of optimization are faced with the tunneling effect of electrons. Physical limitation of excessive leakage current. In order to effectively extend the generational evolution of logic devices, high-permittivity (hereinafter referred to as High-K) materials can effectively reduce the physical limit thickness and have the same equivalent oxide thickness (hereinafter referred to as EOT) Therefore, it can effectively reduce the leakag...

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