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Test structure and method for detecting disc trap and corrosion caused by CMP

A test structure and test line technology, applied in semiconductor/solid-state device testing/measurement, electrical components, electric solid-state devices, etc., can solve problems such as erosion, copper wire sag, and inability to detect at any time, and achieve accurate test results.

Inactive Publication Date: 2011-07-20
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] There are mainly two types of defects in CMP after copper wiring: one of the defects is called a dish defect, referred to as a dish, that is, a depression appears in the copper wire; the other type of defect is erosion, which refers to SiO after polishing in a high pattern density area 2 Part of the dielectric layer is thrown away
However, this type of detection often only detects one area and requires polishing of the chip
This detection method takes a long time and cannot be detected at any time, and the measurement data will be interfered by other factors, resulting in deviation of the test data

Method used

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  • Test structure and method for detecting disc trap and corrosion caused by CMP
  • Test structure and method for detecting disc trap and corrosion caused by CMP
  • Test structure and method for detecting disc trap and corrosion caused by CMP

Examples

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Effect test

Embodiment 1

[0039] In this embodiment, a 0.13 μm copper wiring process is used, and this test structure is used to test the copper wiring on the fourth metal layer caused by the dishing of the copper metal area produced by CMP on the metal block on the first metal layer. influence level.

[0040] from image 3 It can be seen from the figure that the width x1 and length y1 of all the copper metal detection pads in the first copper metal detection pad group 31a and the second copper metal detection pad group 31b are 70 μm. On each metal layer in the chip, the copper metal detection pads of the same size, overlapping and electrically connected to each other are arranged.

[0041] This test structure only comprises a copper metal block stacking unit 32, and described copper metal block stacking unit 32 comprises three continuous, mutually overlapping copper metal blocks from the first layer metal layer to the third layer metal layer, each The width m of the copper metal block is 40 μm, the ...

Embodiment 2

[0047] In this embodiment, the 0.13 μm copper wiring process is adopted, which is mainly used to detect the degree of influence of the erosion of the dielectric region caused by CMP on the first metal layer on the copper wiring on the fifth metal layer.

[0048] from Figure 4 It can be seen from the figure that the width x2 and length y2 of all the copper metal detection pads in the first copper metal detection pad group 41a and the second copper metal detection pad group 41b are 70 μm. On each metal layer in the chip, the copper metal detection pads of the same size, overlapping and electrically connected to each other are arranged.

[0049] This test structure comprises four copper metal block stacking units 42a, 42b, 42c and 42d, and each copper metal block stacking unit includes four consecutive, mutually overlapping For the copper metal block, the length n1 of the metal block in the four copper metal block stacking units is 70 μm, and the widths m1, m2, m3, and m4 are 1...

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Abstract

A test structure for detecting the disc subsidence and erosion caused by a CMP and a method thereof relate to the field of semiconductor manufacturing process. The test structure comprises a first metal detection pad group and a second metal detection pad group, one or a plurality of metal seat stacking units, a first metal test line group and a second metal test line group. The test structure isarranged in the remaining region of the silicon chip. By testing the test structure with an electrical property test method, the invention achieves the aims of detecting the disc subsidence and erosion, and has the advantages of quickness, convenience, accuracy and the like.

Description

technical field [0001] The present invention relates to a semiconductor manufacturing process, in particular to a method for detecting dishing in a metal region and erosion in a dielectric region caused by chemical mechanical polishing (abbreviated as CMP, and the abbreviation CMP is used for chemical mechanical polishing in other parts of the specification). erosion) test structure and method. Background technique [0002] CMP technology has two functions of mechanical grinding of abrasive substances and chemical grinding of acid-base solution. Through CMP, the surface of the wafer can be completely flattened to facilitate subsequent film deposition. [0003] CMP technology is an essential step in existing semiconductor manufacturing processes. However, during the CMP process, defects may be generated due to the different consumption rates of different materials during grinding. [0004] As the number of transistors increases and the interconnecting wires get thinner, the...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/544H01L21/66
Inventor 曾坤赐窦波王奇峰刘勇
Owner SEMICON MFG INT (SHANGHAI) CORP
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