Wide groove shaped polysilicon gate associated transistor

Abstract

The invention discloses a wide groove shape polysilicon conjunction gate transistor; the upper layer of the transistor is a first conductive type high resistivity layer and the lower layer thereof is a first conductive type low resistivity layer; the upper surface of a silicon substrate slice has a plurality of emission zones of the first conductive type with high doping concentration, and a doped polysilicon layer is connected onto each emission zone and also connected with the metal layer of an emitter. The transistor is characterized in that the junction depth of the emission zone is larger than 1 mu m, the junction depth of a substrate area is 4.5-8 mu m, and the junction depth of a groove shape gate area is 6.5-12 mu m; the distance from two adjacent groove shape gate areas with high doping concentration to the interface thereof with the substrate area is less than 2.5 times of the difference between the distance from the bottom of the groove shape gate areas to the upper surface of the silicon substrate slice and the junction depth of the substrate area; and the width of the groove of the groove shape gate area is larger than 3.5 mu m. The invention has the advantages that the current density of the conjunction gate transistor is increased, the uniformity of the current distribution is improved, the capacity for fighting against avalanche breakdown is enhanced, the failure rate in application is lowered by 1-2 orders of magnitude, the production process difficulty is simultaneously reduced, and significant low cost as well as high performance price ratio effectiveness is realized.

Description

technical field [0001] The invention relates to a connected gate transistor, which belongs to the technical field of silicon semiconductor devices. Background technique [0002] In 1979, Hisao Kondo proposed the gate associated transistor GAT (Gate Associated Transistor), followed by a detailed analysis (see IEEETrans.ElectronDevice, v01.ED-27, PP.373-379.1980). In 1994, Chen Fuyuan, Jin Wenxin, and Wu Zhonglong made a further analysis of the connected gate transistor GAT (see "Power Electronics Technology", No. 4, 1994, 1994.11·pp52-55), and pointed out that the connected gate transistor G device exhibits high withstand voltage , fast switching and low saturation pressure drop and other excellent characteristics. [0003] The early connected-gate transistors GAT all adopt planar structure. In 2000, Chinese invention patent ZL00100761.0 (hereinafter referred to as patent 761) proposed a multi-gate transistor with a groove gate polysilicon structure. The principle of the st...

AI Technical Summary

Problems solved by technology

Tie-gate transistors with grooved gate polysilicon structure are often used in circuits with inductive loads such as electronic ballasts for energy-saving lamps. 5-7 times the current, if the slot width is narrow, it will cause more serious current accumulation phenomenon, which will lead to avalanche breakdown in the current accumulation area

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