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Chip package substrate, chip package body, and method for manufacturing chip package body

A technology of chip packaging and manufacturing methods, applied in semiconductor/solid-state device manufacturing, electric solid-state devices, semiconductor devices, etc., can solve problems such as breakage, failure to upgrade, and high cost, so as to reduce costs, increase yields, and be less prone to damage Effect

Inactive Publication Date: 2009-08-26
SUBTRON TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] However, once the thickness of the copper clad substrate 110 becomes too thin, the copper clad substrate 110 will become very fragile, so that it is easily broken by external force.
Therefore, the very thin copper foil substrate 110 cannot use the existing production equipment to cooperate with the current process (such as Figure 1A to Figure 1E Shown) to manufacture, must use special production equipment to manufacture
However, the cost of this special production equipment is very expensive. In addition, this kind of thin copper foil substrate 110 is very fragile and easy to be crushed, punctured or torn by the machine, so that it is easy to be damaged during the production process and cause Yield cannot be improved

Method used

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  • Chip package substrate, chip package body, and method for manufacturing chip package body
  • Chip package substrate, chip package body, and method for manufacturing chip package body
  • Chip package substrate, chip package body, and method for manufacturing chip package body

Examples

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Embodiment Construction

[0078] Figure 2A It is a schematic cross-sectional view of a chip package according to an embodiment of the present invention. See Figure 2A , The chip package 200a includes a circuit substrate 300a, a chip 210, and a packaging glue 220, wherein Figure 2A The circuit substrate 300a shown has a two-layer circuit structure.

[0079] In detail, the circuit substrate 300a includes a conductive pattern layer 310, a first circuit layer 320a, a first dielectric layer 330, and a plurality of first conductive blind hole structures 340a. The conductive pattern layer 310 includes a plurality of first pads 312, and each of the first pads 312 has a bottom surface B. In this embodiment, the conductive pattern layer 310 may only include these first pads 312. In other words, the conductive pattern layers 310 are composed of the first pads 312.

[0080] The first circuit layer 320a is disposed above the conductive pattern layer 310, and the first dielectric layer 330 is disposed between the co...

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PUM

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Abstract

The invention discloses a chip package body, which comprises a circuit substrate, at least one chip and a packaging colloid. The circuit substrate comprises a conductive pattern layer, a circuit layer, a dielectric layer and a plurality of conductive blind hole structures. The conductive pattern layer comprises a plurality of connecting pads. The circuit layer is configured above the conductive pattern layer. The dielectric layer is configured between the conductive pattern layer and the circuit layer and covers all, except the fully exposed bottom surfaces, of the surfaces of the connecting pads. The dielectric layer has a plurality of blind holes. The conductive blind hole structures are arranged in the blind holes respectively. The conductive pattern layer is connected with the circuit through the conductive blind hole structures. The chip is configured on the circuit substrate, and the packaging colloid covers the chip. The invention also discloses a method for manufacturing the chip package body and a chip package substrate.

Description

Technical field [0001] The invention relates to a circuit board, and in particular to a chip package carrier board, a chip package body and a manufacturing method thereof. Background technique [0002] Today's semiconductor technology is advanced, and many chips have a large number of high-density transistors (transistor) elements and many pads arranged on the surface of the chip. In order to be able to package these chips, these chips are usually mounted on a chip package carrier to form a chip package. The current chip package usually uses a copper foil substrate (Copper Clad Laminate, CCL). ) Made. [0003] Figure 1A to Figure 1E It is a schematic flow diagram of a manufacturing method of a known chip package. See Figure 1A versus Figure 1B The manufacturing method of the known chip package includes the following steps. First, a copper foil substrate 110 is provided, which includes a dielectric core layer 112 and two layers of copper foil 114' respectively disposed on two ...

Claims

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Application Information

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IPC IPC(8): H01L23/488H01L23/498H01L23/31H01L21/50H01L21/60H01L21/56
CPCH01L2924/15311H01L2224/73265H01L2224/48227H01L2224/32225H01L24/73H01L2924/181
Inventor 劳绍文
Owner SUBTRON TECH
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