[0078] Figure 2A It is a schematic cross-sectional view of a chip package according to an embodiment of the present invention. See Figure 2A , The chip package 200a includes a circuit substrate 300a, a chip 210, and a packaging glue 220, wherein Figure 2A The circuit substrate 300a shown has a two-layer circuit structure.
[0079] In detail, the circuit substrate 300a includes a conductive pattern layer 310, a first circuit layer 320a, a first dielectric layer 330, and a plurality of first conductive blind hole structures 340a. The conductive pattern layer 310 includes a plurality of first pads 312, and each of the first pads 312 has a bottom surface B. In this embodiment, the conductive pattern layer 310 may only include these first pads 312. In other words, the conductive pattern layers 310 are composed of the first pads 312.
[0080] The first circuit layer 320a is disposed above the conductive pattern layer 310, and the first dielectric layer 330 is disposed between the conductive pattern layer 310 and the first circuit layer 320a. The first dielectric layer 330 has a plurality of first blind holes 332 extending from the first circuit layer 320 a to the conductive pattern layer 310. In addition, the first dielectric layer 330 covers the surfaces other than the bottom surfaces B of the first pads 312, but does not cover the bottom surfaces B.
[0081] In view of the above, in this embodiment, the bottom surface B of the first pads 312 and the surface 334 of the first dielectric layer 330 are substantially aligned. However, the first pads 312 may not be aligned with the surface 334 of the first dielectric layer 330. For example, the first pads 312 may be recessed on the surface 334 of the first dielectric layer 330 due to their thin thickness.
[0082] The first blind conductive via structures 340a are respectively disposed in the first blind holes 332, and the conductive pattern layer 310 is connected to the first circuit layer 320a through the first blind conductive via structures 340a. The first conductive blind hole structures 340a may be located above the first pads 312, that is, the first conductive blind hole structures 340a may be structures in which the blind holes are via in pads.
[0083] The first conductive blind hole structures 340a can be respectively formed conformally in the first blind holes 332 (e.g. Figure 2A Shown). Of course, the first blind conductive via structures 340a may be conductive pillars filling the first blind vias 332.
[0084] The chip 210 is disposed on the circuit substrate 300a and is electrically connected to the circuit substrate 300a. In this embodiment, the chip 210 can be adhered to the circuit substrate 300a, and the first circuit layer 320a includes a plurality of second pads 322 and a plurality of wires 324, wherein the chip 210 is electrically connected through the second pads 322 Connect the circuit board 300a.
[0085] There are many ways to electrically connect the chip 210 to the circuit substrate 300a. Figure 2A The chip 210 shown is electrically connected to the circuit substrate 300a by wire bonding. In detail, the chip package 200a further includes a plurality of bonding wires W, and the chip 210 is connected to the second pads 322 through the bonding wires W, and then electrically connected to the circuit substrate 300a.
[0086] In addition to the above-mentioned wire bonding method, the chip 210 may also adopt a flip chip method or other methods of electrically connecting the circuit substrate 300a. Therefore, it is emphasized here that Figure 2A It is just an example, and does not limit the method of electrically connecting the chip 210 and the circuit substrate 300a.
[0087] The encapsulant 220 is disposed on the circuit substrate 300a and covers the chip 210. When the chip 210 is electrically connected to the circuit substrate 300a by wire bonding, the encapsulant 220 not only covers the chip 210, but also covers the bonding wires W to ensure that the chip 210 can be electrically connected to the circuit substrate 300a normally. Avoid short circuits and open circuits.
[0088] The chip package 200a may further include a plurality of conductive bumps 230, and the conductive bumps 230 are respectively connected to the first pads 312. In detail, the conductive bumps 230 are adhered to the bottom surface B of the first pads 312. The conductive bumps 230 may be solder balls, and the shape of the conductive bumps 230 may be spherical, cylindrical, needle-like, or other suitable shapes.
[0089]In this embodiment, the chip package 200 a may further include a solder mask 350. The solder mask 350 covers the traces 324 of the first circuit layer 320a and exposes the second pads 322. In this way, the solder mask 350 can protect the traces 324 from damage.
[0090] It is worth noting that the upper and lower surfaces of the known chip package are covered by two solder masks respectively (please refer to Figure 1E ), and the two solder mask layers will respectively expose the chip pads on the upper surface and the solder ball pads on the lower surface. However, in this embodiment, the second pads 322 electrically connected to the chip 210 are exposed by the solder mask 350, and the first pads 312 connected to the conductive bumps 230 are formed by the first dielectric layer. 330 exposed.
[0091] Therefore, the first dielectric layer 330 not only provides the function of electrically insulating the conductive pattern layer 310 and the first circuit layer 320a, but also serves as a solder mask for exposing the first pads 312. In addition, the color of the solder mask 350 is usually significantly different from the color of the first dielectric layer 330. Therefore, it can be clearly seen that the colors of the two opposite surfaces of the circuit substrate 300a are different.
[0092] In addition, the solder mask 350 may cover the surrounding area of the top surface of the second pads 322, that is, the solder mask 350 may be of the type of Solder Mask Define (SMD), such as Figure 2A Shown. In other embodiments that are not shown, the solder mask 350 may also be a type of Non-Solder Mask Define (NSMD).
[0093] However, the first dielectric layer 330 only covers the surfaces other than the bottom surfaces B of the first pads 312, and does not cover the bottom surfaces B. In other words, because the first dielectric layer 330 does not cover the bottom surface B of the first pads 312, it does not look like a solder mask defined by a solder mask, and the first dielectric layer 330 is not completely exposed. These first pads 312 are not like solder masks that are not defined by the solder mask.
[0094] In addition, the circuit substrate 300a may further include a plurality of anti-oxidation layers 360, and the anti-oxidation layers 360 are formed on the second pads 322. The anti-oxidation layer 360 can be a nickel-gold layer or made of other anti-oxidation materials, and the function of the anti-oxidation layer 360 is to protect the second pads 322 from oxidation, so as to ensure the electrical connection between the chip 210 and the circuit substrate 300a. The quality of sexual connection.
[0095] Figure 2B It is a schematic cross-sectional view of a chip package according to another embodiment of the present invention. See Figure 2B The chip package 200b of this embodiment is similar to the chip package 200a of the previous embodiment, and the difference between the two is that the circuit substrate 300b of the chip package 200b has a three-layer circuit structure.
[0096] In detail, the circuit substrate 300b includes a conductive pattern layer 310, a first circuit layer 320b, a first dielectric layer 330, these first conductive blind hole structures 340a, a second circuit layer 370, a second dielectric layer 380, and a plurality of The second conductive blind via structure 340b. The second circuit layer 370 is disposed above the first circuit layer 320b of the circuit substrate 300b, and the second dielectric layer 380 is disposed between the first circuit layer 320b and the second circuit layer 370, wherein the second dielectric layer 380 has A plurality of second blind holes 382 extending from the second circuit layer 370 to the first circuit layer 320b.
[0097] The second blind conductive via structures 340b are respectively disposed in the second blind holes 382, and the second circuit layer 370 is connected to the first circuit layer 320b through the second blind conductive via structures 340b. The appearance of the second conductive blind hole structures 340b may be the same as the first conductive blind hole structure 340a, that is, the second conductive blind hole structures 340b may be conformally formed in the second blind holes 382 (e.g. Figure 2B As shown), or the second blind conductive via structures 340b may be conductive pillars filling the second blind vias 382.
[0098] In this embodiment, the second circuit layer 370 includes a plurality of second pads 372 and a plurality of wires 374, and the chip 210 is electrically connected to the circuit substrate 300b through the second pads 372, that is, the chip 210 is electrically connected These second pads 372 are further electrically connected to the circuit substrate 300b. The chip 210 may be electrically connected to the circuit substrate 300b by wire bonding, flip-chip bonding, or other methods. Figure 2B Although the chip 210 shown is electrically connected to the circuit substrate 300b by wire bonding, Figure 2B It is merely an example, and does not limit the manner in which the chip 210 is electrically connected to the circuit substrate 300b.
[0099] See also Figure 2A versus Figure 2B ,It is worth mentioning that, Figure 2A The thickness D1 of the circuit substrate 300a shown can be less than 100 microns, and Figure 2B The thickness D2 of the circuit substrate 300b shown may be less than 150 microns. It can be seen that the chip packages 200a and 200b of this embodiment have a very thin thickness, so the chip packages 200a and 200b are suitable for application in today's portable electronic devices.
[0100] In addition, it must be noted that although Figure 2A The circuit board 300a shown is connected to Figure 2B The circuit substrate 300b shown has a two-layer circuit structure and a three-layer circuit structure, respectively. However, in other unillustrated embodiments, the circuit substrate may also have a four-layer or more than four-layer circuit structure. Therefore, it is particularly emphasized here, Figure 2A versus Figure 2B The disclosed circuit substrates 300a and 300b are all examples and do not limit the number of layers of the circuit structure of the circuit substrate of this embodiment.
[0101] The above only introduces the structure of the chip package of the present invention, and does not introduce the manufacturing method of the chip package of the present invention. In this regard, the following will be Figure 2B The chip package 200b in is taken as an example, and cooperates with Figure 3A to Figure 3L The manufacturing method of the chip package of the present invention will be described in detail. Therefore, it is emphasized that the following Figure 3A to Figure 3L The disclosed manufacturing method of the chip package does not limit the present invention.
[0102] Figure 3A to Figure 3L Yes Figure 2B A schematic cross-sectional view of the manufacturing method of the IC package. See Figure 3A Regarding the manufacturing method of the chip package of this embodiment, first, a carrier substrate 240 and a conductive material layer 310' disposed on the carrier substrate 240 are provided.
[0103] For example, the material of the conductive material layer 310' may be copper, aluminum, aluminum-copper alloy or other appropriate metals, and the carrier substrate 240 may include a first material layer 242 and disposed on the first material layer 242 and the conductive material layer 310 'Between the second material layer 244.
[0104] The material of the first material layer 242 may be metal or ceramic, and the material of the second material layer 244 may be metal or polymer material, wherein the material of the second material layer 244 is different from the conductive material layer 310'. The above-mentioned polymer material is adhesive, that is, the second material layer 244 made of a polymer material can be adhered between the first material layer 242 and the conductive material layer 310'.
[0105] When the first material layer 242 and the second material layer 244 are both metal, the material of the first material layer 242 can be copper, aluminum or other suitable metal materials, and the material of the second material layer 244 can be nickel or other different materials. Metal material on the conductive material layer 310'.
[0106] See Figure 3A versus Figure 3B Next, the conductive material layer 310' is patterned to form a conductive pattern layer 310, wherein the conductive pattern layer 310 is disposed on the carrier substrate 240, and the bottom surface B of each first pad 312 of the conductive pattern layer 310 is opposite to the carrier Substrate 240, such as Figure 3B Shown.
[0107] In view of the above, the method of patterning the conductive material layer 310' may be to perform photolithography and etching processes on the conductive material layer 310'. Since the material of the second material layer 244 is different from the conductive material layer 310', when the conductive material layer 310' is subjected to the etching process, a chemical agent that can only etch the conductive material layer 310' without harming the second material layer 244 can be used . Therefore, the second material layer 244 may serve as an etching stop layer for etching the conductive material layer 310'.
[0108] Next, the circuit substrate 300b is formed (please refer to Figure 3H ) On the carrier substrate 240, wherein the circuit substrate 300b includes a conductive pattern layer 310. Regarding the circuit board 300b, the following will cooperate Figure 3C to Figure 3H Give a detailed explanation. It must be noted in advance that although the circuit substrate 300b has a three-layer circuit structure, the manufacturing method of the chip package of other embodiments not shown can also be used to manufacture a two-layer (such as Figure 2A The circuit substrate 300a) shown is a circuit substrate with a circuit structure of four or more layers of any number of layers.
[0109] For the above, please refer to Figure 3C Regarding the method of forming the circuit substrate 300b, first, a first dielectric layer 330 is formed on the carrier substrate 240, wherein the first dielectric layer 330 covers the carrier substrate 240 and the conductive pattern layer 310. The first dielectric layer 330 can be made of resin, prepreg or other insulating materials, so the first dielectric layer 330 can cover the first pads 312. Next, a first conductive layer 320b is formed on the first dielectric layer 330, wherein the first conductive layer 320b' can be copper foil, aluminum foil or made of other suitable metal materials.
[0110] The first dielectric layer 330 and the first conductive layer 320b' may be formed on the carrier substrate 240 sequentially, that is, the first dielectric layer 330 and the first conductive layer 320b' may not be formed at the same time. Of course, the first dielectric layer 330 and the first conductive layer 320b' can also be formed at the same time. For example, the method of forming the first dielectric layer 330 and the first conductive layer 320b' includes laminating a back adhesive copper foil on the carrier substrate 240.
[0111] See Figure 3D Then, a plurality of first blind holes 332 are formed, wherein the first blind holes 332 extend from the first conductive layer 320b' to the conductive pattern layer 310. In this embodiment, the first blind holes 332 may be formed by a laser drilling process or a plasma etching process. The laser used in the above-mentioned laser drilling process can be a carbon dioxide laser, an ultraviolet-YAG laser or other suitable lasers.
[0112] When the first blind holes 332 are formed by a laser drilling process, some scum from the first dielectric layer 330 will remain at the bottom of the first blind holes 332. These scum will affect the electrical quality of the circuit substrate 300b. Therefore, the manufacturing method of the circuit substrate of this embodiment further includes desmearing the first blind holes 332.
[0113] In addition to the laser drilling process and the plasma etching process, the method for forming the first blind holes 332 can also be to expose and develop the first dielectric layer 330. In detail, the first dielectric layer 330 may be a developable polymer material, that is, the first dielectric layer 330 has photosensitivity. Therefore, these first blind holes 332 can also be formed on the first dielectric layer 330 through exposure and development processes.
[0114] See Figure 3E Next, a plurality of first conductive blind hole structures 340a are formed in the first blind holes 332. These first conductive blind hole structures 340a are connected between the first conductive layer 320b' and the conductive pattern layer 310, that is, the first conductive blind hole structure 340a can electrically connect the first conductive layer 320b' and the conductive pattern layer 310. In addition, these first conductive blind hole structures 340a may be formed by an electroless plating process and an electroplating process.
[0115] See Figure 3E versus Figure 3F After that, part of the first conductive layer 320b' is removed to form the first circuit layer 320b. In this embodiment, the method of removing a part of the first conductive layer 320b' may use photolithography and etching processes. After the first circuit layer 320b is formed, a circuit substrate with a two-layer circuit structure (please refer to Figure 2A ) The manufacturing is generally completed. In other unillustrated embodiments, the subsequent process may include forming a solder mask layer on the first circuit layer 320b, wherein the solder mask layer partially covers the first circuit layer 320b.
[0116] See Figure 3G Then, a second dielectric layer 380 is formed on the first circuit layer 320b. After that, a second conductive layer (not shown) is formed on the second dielectric layer 380. Next, a plurality of second blind holes 382 are formed, wherein the second blind holes 382 extend from the second conductive layer to the first circuit layer 320b. Then, a plurality of second conductive blind hole structures 340b are formed in the second blind holes 382. Then, part of the second conductive layer is removed to form a second circuit layer 370.
[0117] The formation methods of the second dielectric layer 380, the second conductive layer, the second circuit layer 370, the second blind holes 382, and the second conductive blind hole structures 340b are in sequence with those of the first dielectric layer 330 and the first conductive layer. The layer 320b', the second circuit layer 370, the first blind holes 332, and the first conductive blind hole structures 340a are the same, so the description will not be repeated here.
[0118] After the second circuit layer 370 is formed, a circuit substrate 300b with a three-layer circuit structure has been generally manufactured, and a chip package carrier 202 including a circuit substrate 300b and a carrier substrate 240 has also been basically manufactured. The chip package carrier 202 can be manufactured by an upstream circuit board factory, and the chip package carrier 202 will be sent to a downstream chip package factory after the manufacturing is completed for subsequent chip assembly procedures.
[0119] In view of the above, the circuit substrate 300b may further include a solder mask 350. That is, after the second circuit layer 370 is formed, a solder mask 350 may be formed on the second circuit layer 370, wherein the solder mask 350 partially covers the second circuit layer 370 and exposes the second pads 372.
[0120] See Figure 3H In addition, the circuit substrate 300b may also include a plurality of anti-oxidation layers 360. In detail, the anti-oxidation layers 360 can be formed on the second pads 372. In this way, when the chip package carrier 202 is shipped to a downstream chip package factory, the anti-oxidation layers 360 can protect the second pads 372 from oxidation.
[0121] It’s worth mentioning that from Figure 3C to Figure 3H From the disclosed method of forming the circuit substrate 300b, the circuit substrate 300b appears to be manufactured by a build-up method, so the circuit substrate 300b can be manufactured layer by layer. Therefore, the method for forming a circuit substrate of this embodiment can manufacture a circuit substrate with a two-layer circuit structure, and even a circuit substrate with a circuit structure of any number of layers, such as three, four, five, and six layers. .
[0122] In addition, those skilled in the art to which the present invention pertains can learn from Figure 3C to Figure 3H And from the above content, it is known how to manufacture a circuit substrate with a circuit structure of at least two layers or any other number of layers. Therefore, it is emphasized here that Figure 3C to Figure 3H The illustrated manufacturing method of the circuit substrate 300b is not limited to the number of layers of the circuit structure of the manufacturing circuit substrate.
[0123] See Figure 3I Then, the chip 210 is arranged on the circuit substrate 300b, and the chip 210 is electrically connected to the circuit substrate 300b. In this embodiment, the method of electrically connecting the chip 210 to the circuit substrate 300 b may be wire bonding, that is, forming the bonding wires W connected between the chip 210 and the second pads 372. In other embodiments not shown, the method of electrically connecting the chip 210 to the circuit substrate 300b may also be flip-chip bonding or other appropriate methods.
[0124] See Figure 3J Then, an encapsulant 220 is formed on the circuit substrate 300b, wherein the encapsulant 220 covers the chip 210. In this embodiment, the method of forming the encapsulant 220 includes molding and post mold cure (PMC), and the post-mold curing, for example, sends the encapsulant 220 to a temperature of about 180°C. Bake for 4 hours in a good environment. Of course, according to different product requirements, the temperature and time for baking the encapsulant 220 are also different.
[0125] See Figure 3J versus Figure 3K Then, the carrier substrate 240 is removed. In this way, the first dielectric layer 330 can completely expose the bottom surface B of the first pads 312, and a chip package 200b is basically completed.
[0126] Judging from the above content and drawings, the first dielectric layer 330, which can be used as the solder mask of the first pads 312, is not formed by exposure and development processes, and the first dielectric layer 330 does not cover the first pads 312. The bottom surface B of a pad 312 tightly surrounds the sides of the first pads 312.
[0127] Therefore, the first dielectric layer 330 can automatically align the first pads 312 without exposing and developing processes, and does not cover the bottom surfaces B, thereby becoming the solder mask of the first pads 312 . In this way, the first dielectric layer 330 can be said to have a self-aligned structure.
[0128] Regarding the method of removing the carrier substrate 240, when the first material layer 242 and the second material layer 244 are both metal, the method of removing the carrier substrate 240 may be to perform an etching process on the carrier substrate 240. When the second material layer 244 is a viscous polymer material, the method of removing the carrier substrate 240 may include peeling off the first material layer 242.
[0129] See Figure 3K versus Figure 3L The chip package 200b may further include these conductive bumps 230. In detail, after the carrier substrate 240 is removed, the conductive bumps 230 can be formed, and the conductive bumps 230 are respectively connected to the first pads 312. In this way, through these conductive bumps 230, the chip package 200b can be assembled on a circuit board with a larger circuit size such as a motherboard. After the conductive bumps 230 are formed, individual dicing can be performed to form a chip package 200b.
[0130] In summary, by carrying the substrate, the present invention can make the circuit substrate strong, so that the chip package substrate and the chip package body are not easily damaged during the manufacturing process, and can be manufactured with existing production equipment. In this way, the chip package and the chip package carrier of the present invention do not need to be manufactured by special production equipment, so the cost can be reduced, and the yield of the chip package and the chip package carrier can be improved at the same time.
[0131] Secondly, by removing the carrier substrate from the circuit substrate, the present invention can manufacture a chip package with a thinner thickness, and the thickness of the circuit substrate can reach 100 microns or less. Obviously, the chip package and the chip package carrier of the present invention conform to the development trend of portable electronic devices.
[0132] In addition, the first dielectric layer can be used as a solder mask for the first pads, and the first dielectric layer can automatically align the first pads without exposure and development processes, and will not cover the first pads. A pad connects the bottom surfaces of these conductive bumps. Compared with the known method of forming a solder mask, the present invention exposes the solder mask (ie, the first dielectric layer) of the first pads, the production time is shorter, and there is no miss-alignment. ), it can further improve the yield of the chip package and the chip package carrier.
[0133] Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be as defined by the appended claims.
