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Semiconductor memory device and manufacturing method thereof

A manufacturing method and semiconductor technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electric solid-state devices, etc., can solve the problems of reduced capacitive coupling rate of control gate, non-self-alignment of control gate and floating gate, complicated process, etc. , to achieve the effect of increasing storage density, reducing manufacturing cost, and reducing manufacturing cost

Active Publication Date: 2009-10-14
SUZHOU ORIENTAL SEMICONDUCTOR CO LTD
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  • Abstract
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  • Claims
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AI Technical Summary

Problems solved by technology

The disadvantages of this method are as follows: firstly, the photolithography step is used to divide the floating gate, which is expensive and complicated; secondly, the control gate and the floating gate cannot be self-aligned, resulting in a capacitive coupling ratio of the control gate. reduce

Method used

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  • Semiconductor memory device and manufacturing method thereof
  • Semiconductor memory device and manufacturing method thereof
  • Semiconductor memory device and manufacturing method thereof

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Embodiment Construction

[0045] image 3 It is an embodiment of the semiconductor memory device 10 disclosed in the present invention, which is a cross-sectional view along the channel length direction of the device. This device has two floating gates separated by an insulator 304, namely, the floating gate 312 and the floating gate 313. The control gate is composed of a polysilicon layer 303 and a metal layer 302. Above the conductor layer of the control gate is an insulating layer 301. The word line side walls 305 and 311 are insulators such as Si 3 N 4 Materials, they surround the control gate conductor to insulate it from the other conductors of the device. The doping type of the source doped region 314 and the drain doped region 315 is generally opposite to that of the substrate 305. Between the source region and the drain region is the channel 320 of the device. The current between the source doped region 314 and the drain doped region 315 passes along the channel 320, and its density is affected b...

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Abstract

The invention discloses a semiconductor memory device, which comprises a source, a drain, two floating gate regions, a control gate, and a substrate pole, and the floating gate regions of the semiconductor memory device are used for storing charges. The invention further discloses a manufacturing method of the semiconductor memory device. The manufactured semiconductor memory device has the advantages of small unit area, simple manufacturing process and the like, and the use of the invention can reduce the manufacturing cost of a memory chip and improve the storage density.

Description

Technical field [0001] The present invention relates to a semiconductor device, in particular to a semiconductor memory device; the present invention also relates to a semiconductor memory array and a method for manufacturing a chip using this device. Background technique [0002] Semiconductor memory is widely used in various electronic products. With the development of technology, the size of the memory is getting smaller and smaller, and the density is getting higher and higher. In the non-volatile memory, the memory uses the technology of multi-bit storage per cell. For example, a single polysilicon floating gate memory can use multiple threshold voltages to achieve multi-bit storage. Nitrided ROM uses charge trap technology to store two bits in two areas in the silicon nitride medium. The erasing of nitride memory requires hot hole injection, which will affect the reliability of the gate dielectric. As the size of microelectronic devices continues to shrink, the realization ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/112H01L29/788H01L29/423H01L21/8246H01L21/283H10B20/00
Inventor 王鹏飞龚轶张卫
Owner SUZHOU ORIENTAL SEMICONDUCTOR CO LTD
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