Semiconductor device and bias generating circuit

Abstract

There are included a first power supply voltage input part (VDD) that can input a first power supply voltage; a second power supply voltage input part (VDD2) that can input a second power supply voltage; a regulator circuit (11) that generates a back bias voltage based on the second power supply voltage; and an output part (VBP1) that can output, as an output voltage, the back bias voltage generated by the regulator circuit (11). In this way, the generation of a board bias can be achieved with lower power consumption, while the circuit scale can be reduced.

Description

technical field [0001] The present invention relates to a technique for generating a reverse bias voltage involved in a semiconductor device having a logic circuit. Background technique [0002] In recent years, due to advances in the miniaturization of transistors, the leakage current of transistors has increased, and the power consumption of LSI (Large Scale Integration, large scale integrated circuits) has gradually increased. [0003] As one of methods for reducing the leakage current of a transistor, there is known a reverse bias control method of applying a reverse bias (reverse bias, substrate bias) voltage to a substrate of a transistor. [0004] In a conventional substrate bias generating circuit for generating this reverse bias voltage, the reverse bias voltage is generally generated by a clock application type step-up charge pump. [0005] Figure 12 , Figure 13 Each is a diagram showing a configuration example of a clock application type step-up charge pump, ...

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Problems solved by technology

[0008] However, if the LSI is large-scale, the substrate leakage current of the transistor will also increase, and the amount of charge required for application will also increase. However, since the above-mentioned clock application type step-up charge pump drives the capacitor to generate charge by clock application, Therefore, in order to increase the amount of charge, it is necessary to increase the number of circuits or increase the capacity of the capacitor or the clock frequency, which leads to an increase in the scale of the circuit and an increase in the power consumption of the circuit itself.

[0009] That is, in the conventional LSI having a clock application type step-up charge pump, there is a problem that the circuit scale increases or the power consumption of the circuit itself increases.

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