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Semiconductor device and method of manufacturing semiconductor device

A technology for semiconductors and devices, applied in the field of semiconductor devices, can solve the problems of reduced barrier metal film coverage, increased wiring resistance, decreased Cu coverage, etc., and achieves the effects of improving reliability, preventing wiring resistance from increasing, and improving reliability.

Inactive Publication Date: 2010-06-16
RENESAS ELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

If the Ti concentration is too high, a large amount of Ti diffuses into the Cu wiring due to thermal history, which causes the wiring resistance to increase
In addition, since Ti is an element lighter than Ta, the coverage (coverage) of the barrier metal film decreases, a void (hole) occurs between the insulating film and the barrier metal film, and the reliability of Cu wiring decreases
[0007] Meanwhile, if the barrier metal film is formed of only Ta, the adhesion to Cu wiring is low, and the coverage of Cu decreases
For this reason, a void is generated between the Cu wiring and the barrier metal film, and the reliability of the Cu wiring is lowered
In addition, alloying of Cu due to Ti diffusion does not occur, and the reliability of Cu wiring cannot be improved

Method used

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  • Semiconductor device and method of manufacturing semiconductor device
  • Semiconductor device and method of manufacturing semiconductor device
  • Semiconductor device and method of manufacturing semiconductor device

Examples

Experimental program
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Effect test

no. 1 example

[0021] Figures 1A to 1D is a cross-sectional view showing a method of manufacturing the semiconductor device according to the present embodiment. The semiconductor device according to the present embodiment includes: an insulating film 2; a barrier metal film 3 including a trench formed in the insulating film 2 and titanium (Ti) and tantalum ( Ta) alloy; and copper (Cu) wiring 4, which is stacked on the barrier metal film 3 and located in the trench, as Figure 1D shown. The Ti concentration of barrier metal film 3 is equal to or greater than 0.1 at % and equal to or less than 14 at %.

[0022] will use Figures 1A to 1D A method of manufacturing the semiconductor device according to the present embodiment will be described. First, if Figure 1A As shown, a trench 5 is formed in the surface of the insulating film 2 . At this time, as the trench 5, only a wiring trench may be formed or both a via hole and a wiring trench may be formed. If via holes and wiring trenches are...

no. 2 example

[0031] figure 2 is a cross-sectional view showing the configuration of the semiconductor device according to the second embodiment. This semiconductor device has a configuration in which an interlayer insulating layer 30 and an insulating layer 110 are formed on a substrate 10 having a transistor 20 formed thereon, and insulating layers 120, 130, 140 are sequentially stacked. and 150.

[0032] The substrate 10 is, for example, a silicon substrate. The insulating layer 110 has the same configuration as the insulating film 2 in the first embodiment. In the insulating layer 110, Cu wiring 210 is buried. Cu wiring 210 has the same configuration as Cu wiring 4 in the first embodiment. Cu wiring 210 is connected to transistor 20 through a contact buried in interlayer insulating layer 30 . Interlayer insulating layer 30 is made of silicon oxide, for example.

[0033]The insulating layers 120, 130, 140, and 150 have the same configuration as the insulating film 2 in the first e...

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Abstract

A semiconductor device includes an insulating film, a trench which is formed in the insulating film, a barrier metal film which is formed on a sidewall and a bottom surface of the trench, and is composed of an alloy of titanium (Ti) and tantalum (Ta), and a copper (Cu) wiring which is stacked on the barrier metal film, and located in the trench. A titanium concentration of the barrier metal film is equal to or more than 0.1 at % and equal to or less than 14 at %.

Description

[0001] This application is based on Japanese Patent Application No. 2008-292909, the contents of which are incorporated herein by reference. technical field [0002] The present invention relates to a semiconductor device, a method of manufacturing a semiconductor device, and a target for manufacturing a semiconductor device. Background technique [0003] In LSI (Large Scale Integration) wiring, Cu wiring is used. Since Cu easily diffuses into the insulating film, a barrier metal film is formed in the wiring trench before forming the Cu wiring. In this way, Cu can be prevented from diffusing into the insulating layer or the substrate. As the barrier metal film, an alloy of tantalum (Ta) and titanium (Ti) is generally used. [0004] In Japanese Laid-Open Patent Publication No. 2003-109956, a configuration is described in which the Ti ratio in the barrier metal film is equal to or greater than 15 at % and equal to or less than 90 at %. As a result, resistance and stress of ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/532H01L21/768C23C14/14C23C14/34
CPCH01L21/76843H01L23/53295H01L21/2855C23C14/3414H01L23/5283H01L23/53238H01L2924/0002H01L2924/00H01L21/3205H01L21/768
Inventor 本山幸一
Owner RENESAS ELECTRONICS CORP