Semiconductor device and method of manufacturing semiconductor device
A technology for semiconductors and devices, applied in the field of semiconductor devices, can solve the problems of reduced barrier metal film coverage, increased wiring resistance, decreased Cu coverage, etc., and achieves the effects of improving reliability, preventing wiring resistance from increasing, and improving reliability.
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no. 1 example
[0021] Figures 1A to 1D is a cross-sectional view showing a method of manufacturing the semiconductor device according to the present embodiment. The semiconductor device according to the present embodiment includes: an insulating film 2; a barrier metal film 3 including a trench formed in the insulating film 2 and titanium (Ti) and tantalum ( Ta) alloy; and copper (Cu) wiring 4, which is stacked on the barrier metal film 3 and located in the trench, as Figure 1D shown. The Ti concentration of barrier metal film 3 is equal to or greater than 0.1 at % and equal to or less than 14 at %.
[0022] will use Figures 1A to 1D A method of manufacturing the semiconductor device according to the present embodiment will be described. First, if Figure 1A As shown, a trench 5 is formed in the surface of the insulating film 2 . At this time, as the trench 5, only a wiring trench may be formed or both a via hole and a wiring trench may be formed. If via holes and wiring trenches are...
no. 2 example
[0031] figure 2 is a cross-sectional view showing the configuration of the semiconductor device according to the second embodiment. This semiconductor device has a configuration in which an interlayer insulating layer 30 and an insulating layer 110 are formed on a substrate 10 having a transistor 20 formed thereon, and insulating layers 120, 130, 140 are sequentially stacked. and 150.
[0032] The substrate 10 is, for example, a silicon substrate. The insulating layer 110 has the same configuration as the insulating film 2 in the first embodiment. In the insulating layer 110, Cu wiring 210 is buried. Cu wiring 210 has the same configuration as Cu wiring 4 in the first embodiment. Cu wiring 210 is connected to transistor 20 through a contact buried in interlayer insulating layer 30 . Interlayer insulating layer 30 is made of silicon oxide, for example.
[0033]The insulating layers 120, 130, 140, and 150 have the same configuration as the insulating film 2 in the first e...
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Abstract
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