CMOS ultra-wideband prescaler

Abstract

The invention belongs to the technical field of clock frequency division, and in particular relates to a prescaler structure of a phase-locked loop of a CMOS ultra-wideband frequency synthesizer. The prescaler consists of a master differential analogue D latch and a slave differential analogue D latch, wherein each D latch has a pair of differential NMOS tubes serving as a logical part, a pair ofcross-coupled positive feedback NMOS tubes serving as a latch part, two pairs of complementary PMOS tubes working at a positive clock phase and a negative clock phase respectively and serving as a dynamic load, and a pair of clock-controlled NMOS tubes serving as the dynamic bias of the logical part and the latch part respectively. In the invention, the working bandwidth of a circuit is expanded by optimizing methods for reducing an RC constant following a phase output node, increasing the RC constant of a latch phase output node, reducing internal signal excursion and the leakage current loss of a compensated latch phase, and the like; and the ratio of an upper frequency limit to a lower frequency limit of the circuit can reach about 100. The circuit of the invention has the advantages of low power consumption, low noise, wide band, high speed and the like at the same time.

Description

technical field [0001] The invention belongs to the technical field of clock frequency division, and in particular relates to a novel prescaler structure based on a CMOS technology and suitable for a phase-locked loop of an ultra-wideband frequency synthesizer. Background technique [0002] With the development of broadband wireless communication technology, high-performance clock circuit has increasingly become the bottleneck of the further development of this technology. The high-speed prescaler is one of the most critical modules in the phase-locked system of the frequency synthesizer. Its main function is to divide the highest frequency of the system by two and output quadrature I and Q signals as required. In addition, it can divide high-speed non-50% duty cycle signals into 50% duty cycle signals by two. It not only determines the highest operating frequency of the system, but also consumes most of the system power consumption. [0003] At present, high-speed prescal...

AI Technical Summary

Problems solved by technology

[0005] (1) Since the reference clock frequency of the phase-locked loop in the broadband communication system is often relatively low, although the prescaler of this structure can work in the frequency band of several GHz to tens of GHz, it cannot work in the frequency band of the order of megahertz , which brings difficulty to the selection of the reference clock or brings a certain degree of inconvenience to the design

[0006] (2) In high-speed applications, the power consumption of this structure increases significantly with the increase of operating frequency

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