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Semiconductor device

A technology of semiconductors and via holes, which is applied in semiconductor devices, semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, etc., and can solve problems such as poor resistance to external mechanical stress, configuration constraints, and complex manufacturing processes.

Inactive Publication Date: 2010-08-25
SII SEMICONDUCTOR CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] However, in the method of Patent Document 1, an opening hole is formed at the center of the bump electrode, and a conductive layer made of metal or the like is present on the opening hole, so that deformation stress of the bump electrode when mounting a semiconductor device may be easy. Transmitted to semiconductor components, the ability to resist external mechanical stress is poor
[0008] In addition, the manufacturing process of the semiconductor element package at the wafer level as described above is complicated and the process is long, so there is a problem that the manufacturing cost is high.
In addition, in plan view, the rewiring from the input / output metal terminal formed on the semiconductor wafer having the semiconductor element to the bump electrode is formed of metal formed by plating, for example, so that there are restrictions on its arrangement, and the The chip size of the semiconductor element has an influence on

Method used

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  • Semiconductor device
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Embodiment Construction

[0024] Next, use figure 1 and figure 2 A first embodiment of the present invention will be described.

[0025] A semiconductor element 2 constituting a CMOS circuit is formed on a semiconductor substrate 1 made of P-type silicon. An input circuit or an output circuit of a CMOS circuit is connected to an input / output metal terminal 4 through a metal wiring 3 made of aluminum. The uppermost metal wiring 3 and the input / output metal terminals 4 are covered with a protective film 5 made of silicon nitride. In this case, N-type silicon may also be used for the semiconductor substrate 1 .

[0026] Next, the stress buffer layer 6 is formed on the protective film 5 . In this embodiment, a photosensitive polyimide with a thickness of approximately 20 micrometers is formed by spin coating as the stress buffer layer 6 . Thereafter, with respect to the polyimide, the portion of the polyimide serving as the via hole 7 is exposed to light and developed using a photomask, and a hole s...

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Abstract

The present invention has an object to provide a wafer level packaging of a semiconductor element that is simple in manufacturing process and strong against an external mechanical stress. A protection film and a stress buffer layer are formed on a metal wiring formed on a semiconductor element, a via-hole that passes through the protection film and the stress buffer layer is formed so as to expose the metal wiring, and a bump electrode is formed on a conductive layer that fills the via-hole.

Description

technical field [0001] The present invention relates to a semiconductor device having a bump electrode, and relates to a semiconductor device in which a semiconductor element package is formed at a wafer level. Background technique [0002] Figure 5 A cross-sectional view of a conventional wafer-level semiconductor element package is shown. In the case of mounting semiconductor elements at the wafer level, a semiconductor substrate 1 having input / output metal terminals 4 formed on semiconductor elements 2 through metal wiring 3 and protective metal wiring 3 is manufactured. The protective film 5 is etched, and the protective film 5 is etched so that a part of the input / output metal terminal 4 is exposed. Afterwards, the first stress buffer layer 21 is formed on the semiconductor substrate 1, and the first opening hole 23 penetrating the first stress buffer layer 21 is formed on the input-output metal terminal 4 formed on the semiconductor substrate 1, and then, The inner ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/485H01L21/60
CPCH01L2224/05572H01L2924/01015H01L2224/05559H01L2924/01079H01L2224/16H01L2924/01033H01L2224/13027H01L2924/01006H01L2924/01029H01L2224/13099H01L2924/01074H01L2924/01078H01L2924/01022H01L2924/01013H01L2224/13021H01L2924/014H01L2924/01016H01L2924/01024H01L24/12H01L2924/0002H01L2224/0401H01L2224/05647H01L2224/05124H01L2224/05166H01L2224/05147H01L24/05H01L24/13H01L24/03H01L2224/023H01L2924/00012H01L2224/05552H01L2924/00014H01L2924/013H01L2924/0001H01L21/02H01L21/02112
Inventor 近江俊彦
Owner SII SEMICONDUCTOR CORP