Multi-bit width data serial conversion device

Abstract

The invention provides a multi-bit width data serial conversion device which comprises a digital logic module, a PPL (Permutation of Last Layer) module and a first serial conversion module, wherein the digital logic module receives serial data as the even multiple of eight or ten, and converts the serial data as the even multiple of eight into sixteen bit serial data or the serial data as the even multiple of ten into twenty bit serial data under the control of serial interface rate selection signals, bit width selection signals and clock signals; the PPL module generates the clock signals including a sampling clock signal and a synchronous clock signal through a reference clock signal under the control of the serial interface rate selection signals and the bit width selection signals; and the first serial conversion module converts the twenty bit serial data into four bit serial data or the sixteen bit serial data into four bit serial data under the control of the sampling clock signal and the synchronous clock signal. The device realizes serial conversion of data by utilizing simple logic gates and triggers without FIFO (first input first output) circuits, and has a simple structure.

Description

technical field [0001] The invention relates to the technical field of serial data conversion, in particular to a multi-bit wide data serial conversion device. Background technique [0002] In a high-speed serializer and deserializer (HSS, High Speed ​​Serializer and Deserializer) system, signals are often transmitted through capacitor or transformer coupling. Too long a level time will cause the signal level to fade. In this way, the drift of the operating point will be caused at the receiving end of the serializer and the deserializer, and at the same time, the normal operation of the clock data recovery (CDR, Clock and Date Recovery) circuit will be affected due to lack of data conversion. [0003] In order to overcome the above problems, 8B / 10B packet coding is widely used in optical fiber communication and Gigabit Ethernet. 8B / 10B guarantees DC balance, and ensures data conversion by limiting length 0 and length 1. At the same time, due to the introduction of 8B / 10B ...

AI Technical Summary

Problems solved by technology

[0004] However, since the parallel port bit width of the traditional serializer and deserializer analog transmitter is 8bit, when it is necessary to meet the 8B / 10B requirement, it is generally necessary to add a digital first-in-first-out (FIFO, First In First Out) to achieve 10bit to 8bit The conversion, and then send the 8bit digital to the analog transmitter to realize parallel-serial conversion, which increases the difficulty of digital design and increases the chip area

Images