Transistor test device and method

Abstract

The invention provides a transistor test device and method, belonging to the technical field of microelectronics. The transistor test device comprises a routing circuit, a logic gate chain circuit and an output buffer circuit, wherein the routing circuit is used to receive routing signals and input signals and control the paths of the input signals according to the routing signals; the logic gate chain circuit is coupled with the routing circuit and ensures that signals pass through the logic gate chain circuit to form tested signals; the logic gate chain circuit is a cascade circuit composed of an even number of cascaded gate circuits, each gate circuit comprises a transistor to be tested; and the output buffer circuit is coupled with the logic gate chain circuit and the routing circuit respectively and used to receive the middle signals from the logic gate chain circuit or the routing circuit and output the buffered output result. By adopting the technical scheme of the invention, the transistor test device and method are provided, thus solving the test problem of the transistor in packaging mode, monitoring the technology and the structure of the element and testing the transistor conveniently and practically.

Description

technical field [0001] The invention relates to the technical field of microelectronics, in particular to a testing device for a Metal-Oxide-Semiconductor (MOS) transistor. Background technique [0002] At present, MOSFET and related circuits are widely used, among which the complementary MOS (CMOS) process has become the mainstream process in bulk silicon integrated circuit technology due to its advantages of high integration density, low static power consumption, and strong anti-interference ability. [0003] Integrated circuits have developed into the current ultra-large-scale era. To further increase the integration and operating speed of chips, the existing bulk silicon processes are approaching their physical limits. As the feature size of the device shrinks, the interaction between the PN junction inside the device and between the device and the device through the substrate is becoming more and more serious, and a series of new problems in materials, device physics, d...

AI Technical Summary

Problems solved by technology

[0006] The present invention is proposed in view of the cumbersome and complicated problem of CMOS device testing in the related art. Therefore, the main purpose of the present invention is to provide a transistor testing device and method to solve at least one of the above-mentioned problems

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