High-performance field effect transistor and formation method thereof

Abstract

The invention provides a high-performance field effect transistor. The high-performance field effect transistor comprises a substrate, an insulated layer formed on the substrate, and a channel region and a source electrode / drain electrode region which are formed on the insulated layer and a gate stack formed on the channel layer, wherein a carbon-containing thin layer is arranged between the channel region and the source electrode / drain electrode region. The high-performance field effect transistor can effectively inhibit impurities in the source electrode / drain electrode region from spreading into channels by the carbon-containing thin layer such as a Si:C thin layer or a SiGe:C thin layer and inhibit the impurities from spreading toward the substrate by the insulated layer, so that the performance of the transistor is improved.

Description

Technical field [0001] The invention relates to the field of semiconductor technology, in particular to a high-performance field effect transistor and a method for forming the same. Background technique [0002] At present, as the feature size of field effect transistors continues to shrink, high-concentration doped impurities in the source / drain regions will diffuse into the channel in the subsequent high-temperature annealing process, thereby causing deterioration of transistor performance. Therefore, the current doping concentration of impurities in the source / drain regions is limited. For example, the doping concentration of impurity B in strained Si PMOS is lower than 10 21 cm -3 . In addition, if doped polycrystalline Si or polycrystalline SiGe is used as the gate, as the thickness of the gate dielectric layer becomes thinner, high-concentration doped impurities such as B or P can easily penetrate the gate dielectric layer. Reach the channel region, thereby exacerbating th...

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Problems solved by technology

[0002] At present, with the continuous shrinking of the feature size of field effect transistors, the high-concentration doped impurities in the source / drain regions will diffuse into the channel in the subsequent high-temperature annealing process, thereby causing deterioration of transistor performance.

Therefore, the doping concentration of impurities in the source / drain regions is currently limited, for example, the doping concentration of impurity B in strained Si PMOS is lower than 10 21 cm -3

In addition, if doped polycrystalline Si or polycrystalline SiGe is used as the gate, as the thickness of the gate dielectric layer becomes thinner, high-concentration doped impurities such as B or P can easily penetrate the gate dielectric layer. reach the channel region, thereby exacerbating the deterioration of device performance

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