Method for realizing multi-valued resistance memory

Abstract

The invention discloses a method for realizing a multi-valued resistance memory. The method comprises the following steps of: making a resistance memory unit with a sandwich structure consisting of an electrode layer, a resistance conversion layer and an electrode layer in turn; making a plurality of protruding conductive points on an electrode layer surface between the electrode layer and the resistance conversion layer, wherein the conductive points have different heights; and applying different voltages onto the electrode layers on the two sides and forming a point electric field at the conductive points, wherein the electric field induces conductive filaments to form at the points and finally communicate the two electrode layers to realize the multi-valued resistance memory. The method realizes the multi-valued storage of the resistance memory.

Description

technical field [0001] The invention relates to the technical field of information storage, in particular to a method for realizing a multi-valued resistance memory. Background technique [0002] The current mainstream non-volatile memories are all based on floating gate MOS transistor unit structures. It changes the threshold voltage of the MOS transistor by writing or erasing charges in the floating gate, and stores information according to the level of the threshold voltage. The concept of floating gate memory was first proposed by D.Kahng and S.M.Sze in 1967. Based on this concept, the semiconductor industry has successively developed EPROM, EEPROM and the current mainstream FLASH memory. The development of mobile phones, mp3 and various mobile electronic products makes the non-volatile memory of FLASH have a very large market, and this market is still increasing. However, with the technological upgrading and upgrading of the semiconductor industry, the shortcomings of...

AI Technical Summary

Problems solved by technology

However, with the technological upgrading and upgrading of the semiconductor industry, the shortcomings of floating gate memory are becoming more and more obvious.

[0003] First, the floating gate memory will encounter great difficulties in the process of shrinking the 60nm to 45nm process, because its charge writing and erasing mechanism requires the gate to be kept at a certain thickness, which cannot be compared with the device size. shrink together

[0004] Second, the floating gate memory cell uses channel hot electron injection to write charges to the floating gate, and the source-drain voltage must be greater than or equal to 3.2V to enable the channel electrons to obtain enough energy to pass through the tunneling dielectric layer. The power consumption of the floating gate memory is reduced

[0005] Third, the writing and erasing speed of floating gate memory is low, and the current product indicators are all on the order of microseconds, which greatly limits its application range, especially when integrated into embedded systems

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