Method for physically implementing special integrated circuit chip under deep sub-micron

Abstract

The invention provides a method for physically implementing a special integrated circuit chip under deep sub-micron. The method mainly comprises the following steps of: 1) planning layout; 2) laying out; 3) generating a clock tree; 4) wiring; and 5) extracting parameters and analyzing a static time sequence: extracting a parasitic parameter of the layout by adopting a parasitic parameter extraction tool, analyzing the static time sequence, and searching a key path according to the Breadth first search principle. The method has been applied to the practical chip developing process, passed practical tests, and has good practical using effect.

Description

technical field [0001] The invention relates to a physical realization method applied to a special integrated circuit chip in deep submicron, especially relates to a physical realization method under the condition of multiple storage units in the chip. Background technique [0002] At present, the integrated circuit manufacturing process has entered deep submicron, which brings new challenges to the physical realization of ASIC chips. The physical implementation process has a significant impact on timing convergence, and cannot be accurately estimated in the front-end logic design; second, as the feature size continues to shrink, the physical effects of various parasitic parameters have an impact on the correctness and reliability of the design , such as coupling, crosstalk, signal integrity, robustness of electrical and ground networks, etc.; third, the threshold voltage of transistors cannot be scaled down proportionally, the impact of subthreshold current is significant, ...

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Problems solved by technology

[0002] At present, the integrated circuit manufacturing process has entered deep submicron, which brings new challenges to the physical realization of ASIC chips. The physical implementation process has a significant impact on timing convergence, and cannot be accurately estimated in the front-end logic design; second, as the feature size continues to shrink, the physical effects of various parasitic parameters have an impact on the correctness and reliability of the design , such as coupling, crosstalk, signal integrity, robustness of electrical and ground networks, etc.; third, the threshold voltage of transistors cannot be scaled down proportionally, the impact of subthreshold current is significant, and the proportion of leakage power consumption in total power consumption continues to increase

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