Capacitor manufacturing method

Abstract

The invention discloses a capacitor manufacturing method, which comprises the following steps: providing an inter-layer medium layer and an interconnection structure penetrating through the inter-layer medium layer; depositing an etching barrier layer, a first insulating layer, buffer layers and a second insulating layer on the inter-layer medium layer in turn; etching the second insulating layer, the buffer layer and the first insulating layer in turn to form grooves; etching the buffer layers through the grooves so as to increase the local widths of the grooves in the buffer layers; etching the grooves with a first etching agent, so that the bottom widths of the grooves approach to the top widths of the grooves; continuing to etch the grooves with a second etching agent, smoothening the closed angles at the interfaces between the second insulating layer and the buffer layers and between the buffer layers and the first insulating layer, and increasing the groove widths; removing the etching carrier layer; depositing polycrystalline silicon on the inner walls of the grooves and forming semi-spherical polycrystalline silicon particles serving as the lower electrode of the capacitor; and depositing a dielectric layer and an upper electrode on the lower electrode in turn. By using the method, the short circuit and the filling defect between the upper electrode and the lower electrode of the capacitor can be avoided.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a capacitor manufacturing method. Background technique [0002] As the critical dimension of semiconductor devices enters the sub-100nm era, the capacitance and reliability of capacitors play an increasingly important role for traditional single-transistor single-capacitor (1T-1C) structures. There are usually two ways to increase the capacitance of a capacitor. One is to increase the relative area between the upper and lower plates of the capacitor, and the other is to reduce the distance between the upper and lower plates of the capacitor. At present, in the semiconductor manufacturing process, more methods of increasing the relative area between the upper and lower plates of the capacitor are used to increase the capacitance. [0003] For the manufacturing method of capacitors in the existing 1T-1C structure, please refer to the attached Figure 1A to attach Figur...

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Problems solved by technology

[0010] The problem solved by the present invention is that in the existing capacitor manufacturing process, in the cross-sectional area of ​​the first insulating layer and the second insulating layer, the distance between the hemispherical particles used as the lower electrode is too small, and it is difficult to be covered by the dielectric layer in the process of depositing the dielectric layer. Defects that are completely covered, resulting in breakdown of the capacitor

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