Fast reading device and method of phase change memory

A phase change memory and phase change storage technology, applied in the field of micro-nano electronics, can solve problems such as hindering the application of phase change memory and slow reading speed, etc.

Active Publication Date: 2011-04-13
SHANGHAI INST OF MICROSYSTEM & INFORMATION TECH CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Secondly, the larger parasitic capacitance of the bit line makes the reading speed slower, which hinders the application of phase change memory

Method used

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  • Fast reading device and method of phase change memory
  • Fast reading device and method of phase change memory
  • Fast reading device and method of phase change memory

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0034] Please refer to figure 2 As shown, the present invention provides a fast reading device for phase-change memory, which includes a phase-change memory unit 104 to be read, and a charging circuit 101 connected to the phase-change memory unit 104 to be read, for sending a fixed current pulse to the phase-change memory unit to be read Read the phase change memory cell 104 or keep the bit line voltage to a fixed level; the overshoot recovery rate detection circuit 102 connected to the phase change memory cell to be read is used to read the recovery of the bit line level of the phase change memory cell to be read The rate is output in the form of a level; the pull-down bit line circuit 106 connected with the phase-change memory unit to be read is used to quickly pull down the bit-line circuit after the read operation is completed, so that the phase-change memory unit to be read can be read and written next Operation; the sensitive amplifying circuit 103 connected with the ou...

Embodiment 2

[0050] Please refer to Figure 9 As shown, the present invention provides a fast reading device for phase-change memory, which includes a phase-change memory unit 104 to be read, and a charging circuit 101 connected to the phase-change memory unit 104 to be read, for sending a fixed current pulse to the phase-change memory unit to be read Read the phase-change memory cell 104 or keep the bit line voltage to a fixed level; the overshoot recovery rate detection circuit 102 connected to the phase-change memory cell to be read is used to read the bit of the phase-change memory cell to be read in the form of a current slope The recovery rate of the line level is output in the form of a level; the pull-down bit line circuit 106 connected with the phase-change memory unit to be read is used to quickly pull down the bit-line circuit after completing the read operation, so that the phase-change memory unit to be read Carry out next read and write operation; The sensitive amplifying cir...

Embodiment 3

[0053] A fast reading device for phase-change memory, which can compare the recovery rate with a set reference level to determine the state of the phase-change memory unit; it can also compare the recovery rates of two memory units with similar structures, One of them is a memory cell that determines the state, thereby determining the state of the other phase change memory cell. Two memory cells of similar structure, one of which is a phase-change memory cell to be read; the other can be

[0054] b) a resistor with a fixed resistance;

[0055] c) A phase-change memory cell whose state can be determined;

[0056] d) A phase-change memory cell with an undeterminable state.

[0057] The present invention also relates to a reading method of a fast reading device for a phase-change memory unit, which is characterized in that the method includes the following steps:

[0058] 1) Utilize the overshoot recovery rate detection circuit to read the recovery rate after the overshoot of ...

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Abstract

The invention relates to a fast reading device of a phase change memory, which comprises a phase change memory cell to be read, a charging circuit, an overshoot recovery rate detecting circuit, a sensitive amplifier circuit and a reference level or a reference memory cell. On one hand, the phase change memory cell (which can be abstracted as a resistor in the circuit) and a parasitic capacitor ona digit line form a resistor-capacitor (RC) circuit, and on the other hand, a gated metal oxide semiconductor (MOS) pipe instantly enters a linear region from a saturation region when being switched on/of, thereby causing an overshoot phenomenon. For phase change resistors of different states, the corresponding recovery rates after the overshoot are different. By reading the recovery rate of the digit-line level after the overshoot and fast reading the state of the phase change memory cell, the reading rate of the whole memory is accelerated. In addition, fast reading is beneficial to avoiding the damage caused by reading operation to the phase change cell, thereby achieving the purpose of reducing reading interference.

Description

technical field [0001] The invention relates to the technical field of micro-nano electronics, in particular to a novel fast reading method of a phase-change memory. Background technique [0002] Phase change memory technology is based on Ovshinsky's proposal in the late 1960s (Phys. Rev. Lett., 21, 1450-1453, 1968) and early 1970s (Appl. Phys. Lett., 18, 254-257, 1971) The idea that the phase change film can be applied to the phase change storage medium is established, and it is a storage device with low price and stable performance. Phase-change memory can be made on a silicon wafer substrate, and its key materials are recordable phase-change films, heating electrode materials, heat-insulating materials, and lead-out electrode materials. Including how to reduce device material and so on. The basic principle of phase change memory is to use electric pulse signal to act on the device unit, so that the phase change material undergoes reversible phase transition between amor...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C11/56G11C16/26
Inventor 丁晟宋志棠陈后鹏刘波
Owner SHANGHAI INST OF MICROSYSTEM & INFORMATION TECH CHINESE ACAD OF SCI
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