Electrostatic discharge protection circuit

Abstract

The invention relates to an electrostatic discharge protection circuit which comprises a plurality of NMOS (N-type metal-oxide semiconductor) tubes, and gates of the NMOS tubes are grounded and connected in parallel; a drain of each NMOS tube is connected with a bonding pad (Pad), the gates are grounded, sources are grounded, and substrates are grounded; the NMOS tubes are grouped, and each group comprises at least one NMOS tube; and the periphery of the NMOS tube of each group is surrounded by a P-well in a contact manner. The invention relates to the electrostatic discharge protection circuit which comprises a plurality of NFOD (N-type field oxide device) tubes connected in parallel; a drain of each NFOD tube is connected with the bonding pad (Pad), the sources are grounded, and the substrates are grounded; the NFOD tubes are grouped, and each group comprises at least one NFOD tube; and the periphery of the NFOD tube of each group is surrounded by the P-well in a contact manner. Therefore, the difference between parasitic NPN (negative-positive-negative) base resistance positioned at the middle and the parasitic NPN base resistance positioned on two sides in each group is smaller, when ESD (electrostatic discharge) pulses are added on a PAD (portable application description) for generating drain current which flows into the base resistance, all NPN base-emitters are positively biased, and all NPN are in uniform conduction.

Description

technical field [0001] The invention relates to the technical field of electrostatic discharge, and particularly designs an electrostatic discharge protection circuit. Background technique [0002] As the manufacturing process of integrated circuits enters the era of deep sub-micron line width, the MOS elements in integrated circuits adopt lightly doped drain (LDD, Lightly Doped Drain) structure, and the silicide process has been widely used in the diffusion layer of MOS elements superior. At the same time, in order to reduce the diffusion series resistance of the gate polycrystal, a polycrystal compound manufacturing process is adopted. With the shrinking of integrated circuit components, the thickness of the gate oxide layer of MOS components is getting thinner and thinner. The improvement of these manufacturing processes can greatly increase the operation speed inside the integrated circuit and increase the integration level of the circuit. However, these improvements h...

AI Technical Summary

Problems solved by technology

[0009] To sum up, in the above ESD protection circuit, only some of the first NPNs in the middle part are discharging. Since the voltage cannot be higher than the trigger voltage (9.1V) of the NPN, until these NPNs are burned, the NPNs on both sides are also discharged. It cannot be turned on normally, and thus cannot be discharged, so it cannot play the role of ESD protection

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